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mono low - power codec with video buffer http://www.cirrus.com copyright ? cirrus logic, inc., 201 0 C 201 6 (all rights reserved) rev 4. 3 nov 1 6 wm 8944b description the WM8944B is a highly integrated low power hi - fi codec designed for portable devices such as digital still cameras . up to 2 analogue inputs may be connected; a stereo digital microphone interface is also provided. flexible output mixing optio ns support single - ended and differential configurations, with outputs derived from the digital audio paths or from analogue bypass paths. mono line output and mono btl headphone/ speaker drive is supported. flexible digital mixing and powerful dsp functions are available. programmable filters and other processes may be applied to the adc and dac signal paths simultaneously. the dsp functions include 5 notch filters, 5 - band eq, dynamic range control and the retune? feature. the retune? feature is a sophistica ted digital filter that can compensate for imperfect characteristics of the housing, loudspeaker or microphone components in an application. the retune algorithm can provide acoustic equalisation and selective phase (delay) control of specific frequency ba nds. the WM8944B is controlled via a i2c or spi interface. additional functions include digital beep generator, video buff er, programmable gpio functions, frequency locked loop (fll) fo r flexible clocking support and integrated ldo for low noise supply reg ulation. the WM8944B is su pplied in 25 - ball w - csp package, ideal for portable systems. features ? hi - fi audio codec - 94db snr during adc recording (a weighted) - 96db snr during dac playback (a weighted) ? 2 analogue audio inputs ? integrated bias reference for electret microphones ? d igital microphone interface (stereo) ? powerful digital mixing / dsp functions: - 5 - notch filters - 5 - band equalizer (eq) - retune ? parametric filter - dynamic range control and noise gate - low - pass/high - pass filters - direct form 1 (df1) program mable digital filter - 3d stereo enhancement (for digital mic input) ? digital beep generator ? mono line output ? mono btl headphone/ speaker output driver ? i2s digital audio interface - sample rates 8khz to 48 khz ? frequency locked loop (fll) frequency conversion / filter ? video buffer function ? integrated ldo low - noise voltage regulator ? 25 - ball w - csp package ( 2.4 1 x 2.4 1 x 0.55mm , 0.5mm pitch) applications ? digital still cameras (dsc) ? multimedia phones dcvdd dbvdd spkvdd in1/dmicdat adc l aux adc / record digital filters dsp core (l/hpf, 3d surround, 5-notch filter, re-tune eq, dynamic range control) dac digital filters dac l control interface cs/gpio1 sclk sda cifmode/gpio2 fll gpio mclk digital audio interface dacdat adcdat lrclk bclk ldovout gnd vmidc ldovdd digital mic interface -1 digital beep generator dmicclk (gpio) dmicdat vbin vbrefr WM8944B output mixers micbias ldo analogue mic mux / pga spkoutp spkoutn lineout vbout current mode video buffer reference
WM8944B 2 rev 4. 3 table of contents description ................................................................................................................ 1 features ..................................................................................................................... 1 applications .............................................................................................................. 1 table of contents .................................................................................................. 2 bl ock diagram ......................................................................................................... 5 pin configuration ................................................................................................... 6 ordering information ........................................................................................... 6 pin description ......................................................................................................... 7 absolute maximum ratings ................................ ................................................. 8 recommended operating conditions .............................................................. 8 thermal performance .......................................................................................... 9 electrical characteristics ............................................................................ 10 terminology ....................................................................................................................... 13 typical performance .......................................................................................... 14 typical power consumption ........................................................................................ 15 audio signal paths diagram ............................................................................. 16 signal timing requirements ............................................................................. 17 system clock timing ........................................................................................................ 17 audio interface timi ng ................................................................................................... 17 ma ster mode ............................................................................................................................................................................ 17 slave mode ................................................................................................................................................................................ 18 control interface timing ............................................................................................. 19 device description ............................................................................................... 21 introduction ...................................................................................................................... 21 analogue input signal path ......................................................................................... 22 input pga enable .................................................................................................................................................................... 22 input pga configuration .................................................................................................................................................... 23 microphone bias control .................................................................................................................................................. 23 input pga gain contr ol ....................................................................................................................................................... 24 digital microphone interface .................................................................................... 26 analogue- to -digital converter (adc) ...................................................................... 27 adc volume control ............................................................................................................................................................. 28 adc high pass filter ............................................................................................................................................................. 30 dsp core ............................................................................................................................... 31 dsp configuration modes .................................................................................................................................................. 31 low-pass / high-pass filter (lpf/hpf) .............................................................................................................................. 32 3d surround ............................................................................................................................................................................. 33 5-notch filter .......................................................................................................................................................................... 34 df1 filter ................................................................................................................................................................................... 35 hpf ................................................................................................................................................................................................ 35 retune filter ........................................................................................................................................................................... 36 5-band eq .................................................................................................................................................................................... 36 dynamic range control (drc) ........................................................................................................................................... 37 signal enhancement register controls ..................................................................................................................... 37 dynamic range control (drc) ..................................................................................... 38 drc compression / expansion / limiting ......................................................................................................................... 39 gain limits .................................................................................................................................................................................. 43 gain readback ......................................................................................................................................................................... 44 dynamic characterist ics ................................................................................................................................................... 45 anti-clip control ................................................................................................................................................................... 46
WM8944B rev 4. 3 3 quick-release control ....................................................................................................................................................... 47 drc initial conditio n ............................................................................................................................................................. 47 digital- to -analogue converter ( dac) ...................................................................... 48 dac digital volume control .............................................................................................................................................. 48 dac auto-mute ......................................................................................................................................................................... 50 dac sloping stopband filter ............................................................................................................................................ 50 digital beep generat or ................................................................................................ . 51 output signal path .......................................................................................................... 51 output signal paths enable .............................................................................................................................................. 53 line output mixer control ................................................................................................................................................ 54 speaker pga mixer control .............................................................................................................................................. 55 speaker pga volume control ........................................................................................................................................... 56 speaker output contr ol .................................................................................................................................................... 58 analogue outputs ........................................................................................................... 59 line output ............................................................................................................................................................................... 59 speaker outputs .................................................................................................................................................................... 59 external components for line output ........................................................................................................................ 59 ldo regulator ................................................................................................................... 60 reference voltages and master bias ..................................................................... 62 pop suppression control ............................................................................................ 65 disabled output control ................................................................................................................................................... 65 output discharge control ............................................................................................................................................... 65 digital audio interf ace .................................................................................................. 66 master and slave mode operati on ................................................................................................................................ . 66 audio data formats .............................................................................................................................................................. 67 companding .............................................................................................................................................................................. 70 audio interface loopback ................................................................................................................................................. 72 adc to dac loopback ............................................................................................................................................................ 73 digital pull-up and pull-down .......................................................................................................................................... 74 clocking and sample rates .......................................................................................... 74 digital mic clocking .............................................................................................................................................................. 77 frequency locked loop (fll) ............................................................................................................................................ 77 example fll calculation ..................................................................................................................................................... 81 example fll settings ............................................................................................................................................................ 82 video buffer ....................................................................................................................... 83 recommended video buffer initialisation sequences ........................................................................................... 85 general purpose input/output .................................................................................. 87 gpio function select ........................................................................................................................................................... 88 interrupts .......................................................................................................................... 89 control interface ........................................................................................................... 91 selection of control interface mode ......................................................................................................................... 91 2-wire (i2c) control mode ................................................................................................................................................... 92 3-wire (spi) control mode ................................................................................................................................................... 94
WM8944B 4 rev 4. 3 power management ......................................................................................................... 95 thermal shutdown .......................................................................................................... 97 power on reset ................................................................................................................. 97 software reset and device id ..................................................................................... 99 recommended power-up / power-down sequences .............................. 100 register map ......................................................................................................... 102 register bits by add ress ............................................................................................ 107 digital filter characteristics ..................................................................... 152 adc filter response ...................................................................................................... 153 adc highpass filter response .................................................................................. 154 dac filter response ...................................................................................................... 155 video buffer low-pass filter response ............................................................... 157 applications information ............................................................................... 158 recommended external components .................................................................... 158 audio input paths ................................................................................................................................................................ . 158 line output paths ................................................................................................................................................................ 158 btl speaker output connection ................................................................................................................................... 159 power supply decoupl ing ............................................................................................................................................... 159 microphone bias circ uit ................................................................................................................................................... 160 video buffer components ................................................................................................................................................ 161 recommended external components diagram ....................................................................................................... 162 pcb layout considerations ....................................................................................... 162 package dimensions ........................................................................................... 163 important notice ................................................................................................ 164 revision history .................................................................................................. 165
WM8944B rev 4. 3 5 block diagram dcvdd dbvdd spkvdd in1 aux bypass in1/dmicdat inpga adc l aux adc / record digital filters dsp core (l/hpf, 3d, 5-notch filter, re-tune eq, dynamic range control) dac digital filters dac mixspk mixout spkpga + + spkoutp spkoutn lineout control interface cs/gpio1 sclk sda cifmode/gpio2 fll gpio mclk sysclk dacdat adcdat lrclk bclk micbias ldovout gnd vmidc 250k 250k 50k 50k 4k 5k adcref, dacref ldo ldovdd digital mic interface -1 spkoutp spkoutn digital beep generator dmicclk (gpio) dmicdat vbin lpf clamp vbrefr vbout WM8944B ldovdd digital audio interface - + -1 + + + - + - inverted dac dac in1 aux bypass aux/in1 diff inverted dac dac in1 aux bypass aux/in1 diff -57db to +6db in 1db steps -12db to +35.25db in 0.75db steps
WM8944B 6 rev 4. 3 pin configuration the WM8944B is supplied in a 25 -ball csp format. the pin configuration is illustrated below, showing the top -down view from above the chip. ordering information order code temperature range package moisture sensitivity level peak soldering temperature WM8944B ecs/r - 40 ? c to +85 ? c 25 - ball w - csp (pb - free, tape and reel) msl1 260 o c note: reel quantity = 3500 cs/ gpio1 dbvdd dacdat cifmode/ gpio2 vbout mclk vbrefr bclk sclk ldovout lineout spkvdd micbias aux vmidc spkoutp adcdat dcvdd vbin ldovdd in1/ dmicdat sda spkoutn gnd lrclk 1 5 4 3 2 a e d c b top view C WM8944B
WM8944B rev 4. 3 7 pin description pin no name type description a1 spkvdd supply supply for speaker driver a2 lineout analogue output line mixer output a3 vmidc analogue output midrail voltage decoupling capacitor a4 ldovout supply ldo output voltage a5 micbias analogue output microphone bias output voltage b1 spkoutn analogue output negative speaker mixer output b2 spkoutp analogue output positive speaker mixer output b3 aux analogue input aux audio input b4 in1/dmicdat analogue i nput / digital input analogue i nput / digital microphone data input b5 ldovdd supply ldo supply input c1 cifmode/gpio2 digital input / output control interface mode select / gpio2 c2 gnd supply ground c3 sda digital input / output control interface dat a input / output c4 sclk digital input control interface clock input c5 cs /gpio1 digital input / output 3 - wire (spi) control mode chip select / gpio1 d1 bclk digital input / output audio interface bit clock d2 lrclk digital input / output audio interface left / right clock d3 dacdat digital input dac digital audio data input d4 vbrefr analogue output video buffer current reference resistor connection d5 vbout analogue output video buffer output e1 mclk digital input master clock input e2 dbvdd supply digital buffer (i/o) supply e3 dcvdd supply digital core supply e4 adcdat digital output adc / digital microphone digital audio data output e5 vbin analogue input video buffer input
WM8944B 8 rev 4. 3 absolute maximum ratings abs olute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. pr oper esd precautions must be taken during handling and storage of this device. cirrus logic tests its package types according to ipc/jedec j - std - 020 for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 ? ? ? condition min max su pply voltages ( dcvdd ) - 0.3 v 2.5v supply voltages ( ldovdd, dbvdd, spkvdd ) - 0.3 v 4.5v voltage range digital inputs - 0.7 v dbvdd +0.7 v voltage range analogue inputs - 0. 7 v ldo vdd +0. 7 v operating temperature range, t a - 40 o c +85 o c junction temperature, t jmax - 40oc +150oc storage temperature after soldering - 65 o c +150 o c recommended operating conditions parameter symbol min typ max unit digital supply range (core) dcvdd 1. 62 1.8 1.98 v digital supply range (i/o ) dbvdd 1. 62 3.3 3.6 v analogue supply ldovdd 2.4 3.3 3.6 v speaker supply range spkvdd 1.71 3.3 3.6 v grou nd gnd 0 v
WM8944B rev 4. 3 9 thermal performance thermal analysis should be performed in the intended application to prevent the WM8944B from exceeding maximum junction temperature. several contributing factors affect thermal performance most notably the physical properties of the mechanical enclosure, location of the device on the pcb in relation to surrounding components and the number of pcb layers. connecting the gnd balls through thermal vias and into a large ground plane will aid heat extraction. three main heat transfer paths exist to surrounding air as illustrated below in figure 1 : ? package top to air (radiation). ? package bottom to pcb (radiation). ? package balls to pcb (conduction). figure 1 heat transfer paths the temperature rise t r is given by t r = p d * ? ja p d is the power dissipated in the device. ? ja is the thermal resistance from the junction of the die to the ambient temperature and is therefore a measure of heat transfer from the die to surrounding air. ? ja is determined with reference to jedec standard jesd51- 9. the junction temperature t j is given by t j = t a +t r , where t a is the ambient temperature. parameter symbol min typ max unit operating temperature range t a - 40 85 c operating junction temperature t j - 40 1 25 c thermal resistance (junction to board ) ? jb 26 c/w thermal resistance (junction to ambient) ? ja 70 c/w note: 1. junction temperature is a function of ambient temperature and of the device operating conditions. the ambient temperature limits and junction temperature limits must both be observed. w-csp package pcb
WM8944B 10 rev 4. 3 electrical characteristics test conditions dcvdd = 1.8v, dbvdd = ldovdd = spkvdd = 3.3v, ldovout = 3.0v, gnd = 0v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit analogue inputs (in1, aux ) maximum input signal level (changes in proportion to ldovout) single - ended input inpga_vol = 0db 1.0 0 vrms dbv pse udo - differential input inpga_vol = 0db 0.7 - 3.1 vrms dbv input resistance (in1/dmicdat) input pga path (+35.25db) 4.5 k ? ? analogue inputs programmable gain amplifier (pga) minimum programmable gain - 12 d b maximum programmable gain 35.25 db gain step size guaranteed monotonic 0.75 db mute attenuation 92 db c ommon mode rejection ratio 1khz input 110 db speaker output programmable gain amplifier (pga) minimum programmable gain - 57 db maximum programmable gain 6 db gain step size guaranteed monotonic 1 db mute attenuation 71 db adc input path performance (input pga to adc) snr (a - weighted) 84 94 db thd - 1dbfs input - 83 - 72 db thd+n - 1dbfs input - 77 - 70 db psrr (with respect to ldovdd) 217hz , 100mv pk - pk 77 db 1khz , 100mv pk - pk 90
WM8944B rev 4. 3 11 parameter symbol test conditions min typ max unit bypass to line output ( in1 / aux to linemix differential input to lineout , 10k ? / 50pf) snr (a - weighted) inpga _ vol = 0db 90 98 db thd+n inpga_vol = 0db - 89.5 - 80 db bypass to speaker output (in1 /aux to spkmix differential input to spkoutp / spkoutn , 8r btl ) snr (a - weighted) spkvol = 0db 90 96 db thd+n spkvol = 0db - 75 - 65 db dac output path performance (dac to lineout , 10k ? / 5 0pf) maximum output signal level (changes in proportion to ldovout) 1 vrms snr (a - weighted) 85 96 db thd - 80 - 71 db thd+n - 78 - 70 db mute attenuation 125 db psrr (with respect to ldovdd) 217hz , 100mv pk - pk 48 db 1khz , 100mv pk - pk 60 line output resistance 10 k ? dac output path performance (dac to spkoutp or spkoutn , 10k ? / 50pf) maximum output signal level (changes in proportion to ldovout) 1 vrms snr (a - weighted) 85 96 db thd - 78 - 68 db thd+n - 76 - 66 db speaker output performance (speaker output spkoutp/spkoutn , 8 ? btl ) snr (a - weighted) 90 96 db thd p o =150mw 0.03 - 68 % db p o =350mw 2.944 - 30.6 % db thd+n p o =150mw 0.05 - 66 % db p o = 350mw 3.72 - 28.6 % db mute attenuation 92 db psrr (with respect to ldovdd) 217hz 48 db 1khz 60 psrr (with respect to spkvdd) 217hz , 100mv pk - pk 89 db 1khz , 100mv pk - pk 79 speaker resistance 8 ?
WM8944B 12 rev 4. 3 parameter symbol test conditions min typ max unit digital inputs/outputs input high level 0. 7 ? dbvdd v input low level 0. 3 ? dbvdd v output high level i ol = 1ma 0. 8 ? dbvdd v output low level i oh = - 1ma 0. 2 ? dbvdd v input capacitance 10 pf input leakage all digital pins except cifmode - 900 900 na cifmode pin - 90 90 ua ldo regulator input voltage ldovdd 2.4 3.3 3.6 v output voltage ldovout ldo_ref_sel = 0 3.0 v dropout voltage ldovdd - ldovoutldovdd - ldovout i load =50ma, ldovout>2.4v 200 mv i load =50ma, ldo vout 2.4v 400 mv maximum output current (see note) 50 ma output voltage accuracy i load = 50ma 2 % quiescent current no load 55 ? a leakage current 1 ? a psrr (with respect to ldovdd) 217hz, 100mv pk - pk 40 db 1khz, 100mv pk - pk 49 video buffer maximum output voltage swing vom f=100khz, thd=1% 1.10 1.25 1.50 v pk - pk voltage gain av vb_gain = 1, r ref =187 ? , r load =75 ? , r source =75 ? 5.08 6 7.94 db vb_gain = 0, r ref =187 ? , r load =75 ? , r source =75 ? - 0.92 0 1.94 db gain step siz e 6 db differential gain dg vin = 1v pk - pk - 2.0 0.3 +2.0 % differential phase dp vin = 1v pk - pk - 2.0 0 +2.0 deg snr vsnr 40 60 100 db sync tip offset above gnd vb _pd = 0 vb_gain = 1 (+6db) 0 40 75 mv third order low pass filter response (referen ced to 100khz) r ref =187 ? , r load =75 ? , r source =75 ? , 0db gain 2.4mhz - 0. 5 0 0. 5 db 5.13mhz - 0.5 - 0.2 0. 5 db 9.04mhz - 3.0 - 1.6 0 db 13.32mhz - 11.0 - 7.0 - 3.0 db psrr (with respect to ldovdd) psrr 100khz , 50mv pk - pk 60 db clocking mclk fre quency 30hz 27mhz hz fll output frequency 2.045 50 mhz fll lock time 2 ms
WM8944B rev 4. 3 13 parameter symbol test conditions min typ max unit micbias bias voltage (changes in proportion to ldovout) micbias micb_lvl = 0 2.55 2.7 2.85 v micb_lvl = 1 1.95 v bias current source v micbias within +/ - 3 % 3 ma output noise spectral density 1khz to 20khz 40 nv/ ? bandgap reference bandgap voltage - 10% 1.5 +10% v analogue reference levels midra il reference voltage (changes in proportion to ldovout) vmid vmid_ref_sel = 1 vmid_ctrl=1 1.5 v bandgap reference bg_vsel=01010 - 10% 1.5 +10% v note : the maximum ldo output current is the total internal and external load capability; internal circuits of the WM8944B will typically account for 25ma of this capacity. terminology 1. signal- to -noise ratio (db) C snr is the difference in level between a full scale output signal and the device output noise with no signal applied, measured over a bandwidth of 20hz to 20khz. this ratio is also called idle channel noise. (no auto-zero or mute function is employed). 2. total harmonic distortion (db) C thd is the difference in level between a 1khz reference sine wave output signal and the first seven harmonics of the output signal. the amplitude of the fundamental frequency of the output signal is compared to the rms value of the next seven harmonics and expressed as a ratio. 3. total harmonic distortion plus noise (db) C thd+n is the difference in level between a 1khz reference sine wave output signal and all noise and distortion products in the audio band. the amplitude of the fundamental reference frequency of the output signal is compared to the rms value of all other noise and distortion products and expressed as a rat io. 4. mute attenuation C this is a measure of the difference in level between the full scale output signal and the output with mute applied. 5. power supply rejection ratio (db) C psrr is a measure of ripple attenuation between a power supply rail and a signal output path. with the signal path idle, a small sine wave ripple is applied to power supply rail. the amplitude of the supply ripple is compared to the amplitude of the output signal generated and is expressed as a ratio. 6. all performance measurements are carried out with 20khz aes17 low pass filter for distortion measurements, and an a-weighted filter for noise measurement. failure to use such a filter will result in higher thd and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out- of -band noise; although it is not audible, it may affect dynamic specification values.
WM8944B 14 rev 4. 3 typical performance wm 8944 b _ in 1 _ adc _ thd + nvsampl - 110 wm 8944 b _ dac _ lineout _ thd + nvsampl - 110 wm 8944 b _ dac _ spkout _ 8 btl _ 350 mw _ thd + nvsampl - 110 t
WM8944B rev 4. 3 15 typical power consumption dcvdd dbvdd ldovdd spkvdd total (ma) power (mw) (ma) (ma) (ma) (ma) condition 1.8 3.3 3.3 3.3 powerdown supplies are all off except spkvdd -- -- -- 5.776e - 05 -- 0.000 powerdown (register settings are default value, no mclk , therr_act=0, cifmode/gpio2 configured as an input ) 0.0016 0.007 0.00717 0.00133 0.0 17 0.05 4 powerdown (register settings are default value, mclk=12.288mhz, therr_act=0, cifmode/gpio2 configured as an input) 0.113 0.012 0.00679 0.00138 0.133 0.270 powerdown (register settings are default value, mclk=24.576mhz, therr_act=0, cifmode/gpio2 config ured as an input) 0.245 0.017 0.00717 0.00133 0. 271 0.525 playback playback to lineout (se_config=dsp playback, no data) 2.55 0.127 1.5 0.00146 4.18 9.964 playback to speaker 8ohm btl (se_config=dsp playback, no data) 2.55 0.127 1.64 5.48 9.8 0 28.505 playback (low vmid) playback to speaker 8ohm btl with low vmid (se_config=dsp playback, no data) 2.55 0.127 1.99 5.32 9.9 9 29.132 record in1 to record (se_config=dsp record, no data) 2.85 0.127 3.87 0.00134 8.7 18.325 record and playback in1 to record + playback to lineout + speaker 8ohm btl + micbias (se_config=dsp playback / record, no data) 4.01 / 5.03 0.126 6.22 5.48 15.8 46.2 / 48.1 in1 to record + playback to lineout + speaker 8ohm btl + micbias + fll (se_config=dsp playback / record, no data) 5 .32 / 6.29 0.265 6.22 5.48 17.3 49.1 / 50.8 in1 to record + playback to lineout + speaker 8ohm btl + micbias + fll + video buffer (se_config=dsp playback / record, no data) 5.32 / 6.29 0.264 7.21 5.48 18.3 52.3 / 54.1 record and playback (low vmid) in1 to record + playback to lineout + speaker 8ohm btl with low vmid + micbias + fll + video buffer (se_config=dsp playback / record, no data) 5.32 / 6.27 0.264 7.56 5.32 18.5 53.0 / 54.7 in1 to record + playback to lineout + speaker 8ohm btl with low vmid + micbias + fll + video buffer + bandgap (se_config=dsp playback / record, no data) 5.30 / 6.27 0.265 7.5 5.31 18.4 52.7 / 54.4
WM8944B 16 rev 4. 3 audio signal paths diagram dcvdd dbvdd spkvdd in1 aux bypass in1/dmicdat inpga adc l aux adc / record digital filters dsp core (l/hpf, 3d, 5-notch filter, re-tune eq, dynamic range control) dac digital filters dac mixspk mixout spkpga + + spkoutp spkoutn lineout control interface cs/gpio1 sclk sda cifmode/gpio2 fll gpio mclk sysclk dacdat adcdat lrclk bclk micbias ldovout gnd vmidc 250k 250k 50k 50k 4k 5k adcref, dacref ldo ldovdd digital mic interface -1 spkoutp spkoutn digital beep generator dmicclk (gpio) dmicdat vbin lpf clamp vbrefr vbout WM8944B ldovdd digital audio interface inpga_ena micb_ena micb_lvl inpga_vol[5:0] adcl_vol[7:0] adc_hpf_mode adc_hpf_sr[1:0] adc_hpf_cut[1:0] adc_hpf dac_vol[7:0] dac_sb_flt spk_vol aux_to_spkp spkn_spkvdd_ena spkn_op_ena aux_to_n_inpga p_inpga_sel[1:0] adcl_ena dac_ena beep_gain[3:0] beep_rate[1:0] beep_ena in1_to_spkn out_ena spk_mix_ena spk_pga_ena pga_to_spkp pga_to_spkn byp_to_out mdac_to_out dac_to_out in1_to_out aux_to_out byp_to_pga mdac_to_pga dac_to_pga in1_to_pga aux_to_pga line_mute spk_mix_mute spkn_op_mute spkp_spkvdd_ena spkp_op_ena spkp_op_mute dmic_ena - + -1 + + auxdiff_to_out auxdiff_to_pga + - + -
WM8944B rev 4. 3 17 signal timing requirements system clock timing figure 2 master clock timing test conditions dcvdd = 1.8v, dbvdd = ldovdd = spkvdd = 3.3v, ldovout = 3.0v, gnd = 0v, t a = +25 o c . parameter symbol conditions min typ max unit master clock timing mclk cycle time t mclky 0.037 ? mclkh : t mclkl ) 60:40 40:60 audio interface timi ng master mode figure 3 audio interface timing - master mode test conditions dcvdd = 1.8v, dbvdd = ldovdd = spk vdd = 3.3v, ldovout = 3.0v, gnd = 0v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24 - bit audio data unless otherwise stated. parameter symbol min typ max unit audio interface timing - master mode lrclk propagation delay from bclk falling edge t dl 20 ns adcdat propagation delay from bclk falling edge t dda 20 ns dacdat setup time to bclk rising edge t dst 20 ns dacdat hold time from bclk rising edge t dht 10 ns mclk t mclkl t mclkh t mclky bclk (output) adcdat lrclk (output) t dl dacdat t dda t dht t dst
WM8944B 18 rev 4. 3 slave mode figure 4 audio interface timing C slave mode test conditions dcvdd = 1.8v, dbvdd = ldovdd = spkvdd = 3.3v, ldovout = 3.0v, gnd = 0v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24 - bit audio data unless otherwise stated. parameter symbol min typ max un it audio interface timing - slave mode bclk cycle time t bcy 50 ns bclk pulse width high t bch 20 ns bclk pulse width low t bcl 20 ns lrclk set - up time to bclk rising edge t lrsu 20 ns lrclk hold time from bclk rising edge t lrh 10 ns dacdat ho ld time from bclk rising edge t dh 10 ns adcdat propagation delay from bclk falling edge t dd 20 ns dacdat set - up time to bclk rising edge t ds 20 ns note: bclk period must always be greater than or equal to mclk period. bclk (input) lrclk (input) adcdat (output) dacdat (input) t ds t dd t dh t lrh t lrsu t bch t bcl t bcy
WM8944B rev 4. 3 19 control interface timing figure 5 control interface timing - 2-wire (i2c) control mode test conditions dcvdd = 1.8v, dbvdd = ldovdd = spkvdd = 3.3v, ldovout = 3.0v, gnd = 0v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0 db, 24 - bit audio data unless otherwise stated. parameter symbol min typ max unit sclk frequency 400 khz sclk low pulse - width t 1 1300 ns sclk high pulse - width t 2 600 ns hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sda, sclk rise time t 6 300 ns sda, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 0 5 ns sclk (input) sda t 4 t 3 start t 8 stop t 5 t 2 t 1 t 9 t 7 t 6
WM8944B 20 rev 4. 3 figure 6 control interface timing - 3-wire (spi) control mode (write cycle) note: the data is latched on the 32 nd falling edge of sclk after 32 bits have been clocked into the device. figure 7 control interface timing - 3-wire (spi) control mode (read cycle) test conditions dcvdd = 1.8v, dbvdd = ldovdd = spkvdd = 3.3v, ldovout = 3.0v, gnd = 0v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24 - bit audio data un less otherwise stated. parameter symbol min typ max unit cs falling edge to sclk rising edge t csu 40 ns sclk fall ing edge to cs rising edge t cho 10 ns sclk pulse cycle time t scy 200 ns sclk pulse width low t scl 80 ns sclk pulse width high t sch 80 ns sd a to sclk set - up time t dsu 40 ns sda to sclk hold time t dho 10 ns pulse width of spikes that will be suppressed t ps 0 5 ns sclk falling edge to sda output transition t dl 40 ns cs (input) sclk (input) sda (input) t csu t cho t sch t scl t scy t dho t dsu sclk (input) sda (output) t dl cs (input)
WM8944B rev 4. 3 21 device description introduction the WM8944B is a highly integrated low power hi-fi codec designed for portable devices such as digital still cameras and multimedia phones. flexible analogue interfaces and powerful digital signal processing (dsp) in a 2.41 x 2.41m m footprint make it ideal for small portable devices. the WM8944B supports up to 2 analogue audio inputs. one single-ended or pseudo differential microphone / line input may be selected as the adc input source. the analogue inputs can also be configured as inputs to the output mixers, either as two single ended inputs or as a differential pair . an integrated bias reference is provided to power standard electret microphones. a stereo digital microphone interface is also supported, with direct in put to the dsp core . the hi - fi adc and dac operate at sample rates from 8khz up to 48khz. a high pass filter is available in the adc path for removing dc offsets and suppressing low frequency noise such as mechanical vibration and wind noise. a digital tone (beep) generator allows au dio tones to be injected into the dac output path. the WM8944B provides a powerful dsp capability for configurable filtering and processing of the digital audio path. the dsp provides low-pass / high-pass filtering, notch filters, 5- band eq, dynamic range control (drc) and a programmable df1 digital filter. the tuned notch filters allow narrow frequency bands to be attenuated, to provide filtering of motor noise or other unwanted sounds ; the 5- band eq allows the signal to be adjusted for user-preferences. the dynamic range control provides a range of compression, limiting and noise gate functions to support optimum configuration for recording or playback modes. the df1 filter allows user-specified filters to be implemented in the digital signal chain. 3d stereo enhancement is provided; this may be used on the stereo digital microphone input path. the retune ? feature is a highly-configurable dsp algorithm which can be tailored to cancel or compensate for imperfect characteristics of the housing, loudspeaker or microphone components in the target application. the retune algorithm coefficients and register contents are calculated using cirrus logics wisce? software; lab bench tests and audio reference measurements must be performed in order to determine the optimum settings. the digital signal routing between the adc, dac and i2s digital audio interface can be configured in different ways according to the application requirements. the dsp functions may be applied to the adc record path, the dac playback path , or split between the two paths (refer to the dsp configuration modes section). two analogue output mixers are provided, connected to 3 analogue output pins . a mono line output and mono btl speaker may be connected to these outputs. the WM8944B incorporates an ldo regulator for compatibility with a wide range of supply rails; the internal ldo can also reduce any interference resulting from a noisy supply rail. the ldo regulator can also be used to provide a regulated supply voltage to other circuits. i2c or spi control interface modes for read/write access to the register map. a single external clock provides timing reference for all the digital functions; an integrated frequency locked loop (fll) also provides flexibility to perform frequency conversions and to remove noise/jitter from the external clock. the fll can be configured for reduced power consumption, or for different filtering requirements of the reference source. additional functions include a current-mode video buffer providing excellent video signal reproduction at low operating voltages. up to 2 gpio pins may be configured for miscellaneous input/output, or for status indications from the temperature monitoring functions.
WM8944B 22 rev 4. 3 analogue input signal path the WM8944B has two analogue input pins, which may be selected in different configurations. the analogue input paths can support line and microphone inputs, in single-ended or pseudo-differential modes. the analogue inputs in1/dmicdat aux may be configured as inputs to the input pga or to the output mixe rs as single- ended or differential signals . the input pga (pga) is routed to the analogue to digital converter (adc). there is also a bypass path, enabling the signal to be routed directly to the output mixers. the WM8944B input signal paths and control registers are illustrated in figure 8 . figure 8 input signal paths input pga enable the input pga (programmable gain amplifier) is enabled using the register bit inpga_ena, as described in table 1 . register address bit label default description r2 (02h) power management 1 12 inpga_ena 0 input pga enable 0 = disabled 1 = enabled table 1 input pga enable to enable the input pga, the reference voltage vmid and the bias current must also be enabled. see reference voltages and master bias for details of the associated controls vmid_sel and bias_ena. WM8944B in1/dmicdat inpga aux digital mic interface dmicclk (gpio) dmicdat inpga_ena inpga_vol[5:0] adcl_vol[7:0] adc_hpf_mode adc_hpf_sr[1:0] adc_hpf_cut[1:0] adc_hpf aux_to_n_inpga p_inpga_sel[1:0] adcl_ena dmic_ena - + in1 aux bypass adc l adc / record digital filters
WM8944B rev 4. 3 23 input pga configurat ion microphone and line level audio inputs can be connected to the WM8944B in single-ended or differential configurations. (these two configurations are illustrated in figure 55 and figure 56 in the section describing the external components requirements - s ee applications information .) for single-ended microphone inputs, the microphone signal is connected to the non -inverting input of the pga (in1/dmicdat), whilst the inverting input of the pga is connected to vmid. for differential microphone inputs, the non-inverted microphone signal is connected to the non -inverting input of the pga (in1/dmicdat) , whilst the inverted (or noisy ground) signal is conne cted to the inverting input pin (aux). line level inputs are connected in the same way as a single- ended microphone signal. the non -inverting input of the pga (in1/dmicdat) is configured using the p_ in pga_sel register bit. this register allows the selection of the two possible input pins to the pga. the inverting input is configured using the aux_to_n_inpga register bit. the registers for configuring the input pga are described in table 2 . register address bit label default description r39 (27h) input ctrl 9 aux_to_n _ inp ga 0 input pga inverting input selec t 0 = connected to vmid 1 = connected to aux 1:0 p_ in pga_sel [1:0] 01 input pga non - inverting input select 00 = reserved 01 = connected to in1/dmicdat 10 = connected to aux 11 = reserved table 2 input pga configuration micropho ne bias control the WM8944B provides a low noise reference voltage suitable for biasing electret condenser (ecm) type microphones via an external resistor. refer to the applications information section for recommended components. the micbias voltage is enabled using the micb_ena register bit; the voltage can be selected using the micb_lvl bit, as described in table 3 . register address bit label default description r2 (02h) power management 1 4 micb _ena 0 mic rophone b ias e nable 0 = d isabled 1 = e nabled r39 (27h) input ctrl 6 micb_lvl 0 mic rophone b ias v oltage control 0 = 0.9 x ldo v out 1 = 0.65 x ldo v out table 3 microphone bias control
WM8944B 24 rev 4. 3 input pga gain contr ol the volume control gain for the pga is adjuste d using the in pga_vol register field as described in table 4 . the gain range is -12db to +35.25db in 0.75db steps. the gains on the inverting and non- inverting inputs to the pga are always equal. the input pga can be muted using t he inpga_mute mute bit. to prevent "zipper noise", a zero-cross function is provided on the input pga. when this feature is enabled, volume updates will not take place until a zero-crossing is detected. the input pga volume control register fields are described in table 4 . register address bit label default description r40 (28h) input pga gain ctrl 7 inpga_zc 0 input pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 6 in pga_mute 1 input pga m ute 0 = disable mute 1 = enable mute 5:0 in pga_vol [5:0] 01_0000 (0db) input pga volume 00_0000 = - 12db 00_0001 = - 11.25db table 4 input pga volume control
WM8944B rev 4. 3 25 in pga_vol[5:0] volume ( d b) in pga_vol[5:0] volume ( d b) 00_0000 - 12 10_0000 12 00_0001 - 11.25 10_0001 12.75 00_0010 - 10.5 10_0010 13.5 00_0011 - 9.75 10_0011 14.25 00_0100 - 9 10_0100 15 00_0101 - 8.25 10_0101 15.75 00_0110 - 7.5 10 _0110 16.5 00_0111 - 6.75 10_0111 17.25 00_1000 - 6 10_1000 18 00_1001 - 5.25 10_1001 18.75 00_1010 - 4.5 10_1010 19.5 00_1011 - 3.75 10_1011 20.25 00_1100 - 3 10_1100 21 00_1101 - 2.25 10_1101 21.75 00_1110 - 1.5 10_1110 22.5 00_1111 - 0.75 10_1111 23.25 01_0000 0 11_0000 24 01_0001 0.75 11_0001 24.75 01_0010 1.5 11_0010 25.5 01_0011 2.25 11_0011 26.25 01_0100 3 11_0100 27 01_0101 3.75 11_0101 27.75 01_0110 4.5 11_0110 28.5 01_0111 5.25 11_0111 29.25 01_1000 6 11_1000 30 01_1001 6.75 11_1001 30.7 5 01_1010 7.5 11_1010 31.5 01_1011 8.25 11_1011 32.25 01_1100 9 11_1100 33 01_1101 9.75 11_1101 33.75 01_1110 10.5 11_1110 34.5 01_1111 11.25 11_1111 35.25 table 5 input pga volume range
WM8944B 26 rev 4. 3 digital microphone interface the wm8 944b supports a stereo digital microphone interface, using the in1 /dmicdat input pin for data and a gpio pin for the data clock. the analogue signal path from the in1 /dmicdat pin must be disabled when using the digital microphone interface; this is achieved by disabling the input pga, (ie. inpga_ena = 0). note that, although the WM8944B is largely a mono device, it supports a stereo signal path from the digital microphone interface to the digital audio interface. dsp processing, including 3d stereo enhancement, can be enabled on this signal path - see the dsp core section. the digital microphone input, dmicdat, is provided on the in1/dmicdat pin. the associated clock, dmic clk , is provided on a gpio pin. the digital microphone input is selected as input by setting the dmic_ena bit. when the digital microphone input is selected, the adc input is deselected. the digital microphone interface configuration is illustrated in figure 9 . note that the digital microphone may be powered from micbias or from ldovout; care must be taken to ensure that the respective digital logic levels of the microphone are compatible with the digital input thresholds of the WM8944B. the digital input thresholds are referenced to dbvdd, as defined in electrical characteristics. figure 9 digital microphone interface when any gpio pin is configured as dmic clk output, the WM8944B outputs a clock which supports digital mic operation at the adc sampling rate. the adc and record path filters must be enabled and the adc sampling rate must be set in order to ensure correct operation of all dsp functions associated with the digital microphone. volume control for the digital microphone interface signals is provided using the adc volume control. the WM8944B supports stereo digital microphone operation. the adcl_ena register enables the left channel; the adcr_ena register enables the right channel. note that only the digital blocks are enabled by the adcr_ena register. see analogue-to-digital converter (adc) for details of the adc enable and volume control functions. see general purpose input/output for details of configuring the dmicclk output. see clocking and sample rates for the details of the sample rate control. when the dmic_ena bit is set, then the in1 pin is used as the digital microphone input dmicdat. up to two microphones can share this pin; the two microphones are interleaved as illustrated in figure 10. the digital microphone interface requires that mic1 (left channel) transmits a data bit each time that dmicclk is high, and mic2 (right channel) transmits when dmicclk is low. the WM8944B samples the digital microphone data in the middle of each dmicclk clock phase. each microphone must tri-state its data output when the other microphone is transmitting. drc input pga micbias dmic dmicdat dmicclk micbias digital audio interface (adcdat) adc volume hpf dmic_ena gpion in1/ dmicdat decimation adc dmic interface gpio adcl_ena adcr_ena sr[3:0] inpga_ena=0
WM8944B rev 4. 3 27 figure 10 digital microphone interface timing the digital microphone interface control fields are described in table 6 . register address bit label default description r2 (02h) power management 1 7 dmic_ena 0 enables digital microphone mode 0 = audio dsp input is from adc 1 = audio dsp input is from digital microphone interface when dmic_ena = 0 , the digital microphone clock (dmic clk ) is held low. table 6 digital microphone interface control analogue-to-digital converter (adc) the WM8944B uses a 24 -bit sigma-delta adc. the use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. the adc full-scale input level is proportional to ldo vout . see electrical characteristics section for further details. any input signal greater than full scale may overload the adc and cause distortion. the adc and associated digital record filters are enabled by the adcl_ena register bit. the adc digital blocks are also required for the digital microphone interface; the left and right digital microphone paths are enabled by adcl_ena and adcr_ena respectively. register address bit label default description r2 (02h) power management 1 11 adcr_ena 0 right adc enable 0 = disabled 1 = enabled adcr _ena must be set to 1 when processing right channel data from the digital microphone. 10 adcl_ena 0 left adc enable 0 = disabled 1 = enabled adcl_ena must be set to 1 when processing data from the adc or from the left digital microphone. table 7 adc enable control dmicclk pin dmicdat pin (left/right channels interleaved) 1 2 1 2 1 2 mic1 output (left channel) 1 1 1 mic2 output (right channel) 2 2 2 hi-z
WM8944B 28 rev 4. 3 adc volume control the output of the adc (or digital microphone interface) can be digitally amplified or attenuated over a range from - 71.625db to +23.625 db in 0.375db steps. the volume of each channel is controlled us ing adcl_vol or adcr_vol . the adc volume is part of the adc digital filters block. the gain for a given eight-bit code x is given by: 0.375 ? (x -192) db for 1 ? x ? 255 ; mute for x = 0 the adc_vu bit controls the loading of digital volume control data. when adc_vu is set to 0, the adcl_vol or adcr_vol control data is loaded into the respective control register, but does not actually change the digital gain setting. both left and right gain settings are updated when a 1 is written to adc_vu. this makes it possible to update the gain of both channels simultaneously. the output of the adc or digital microphone (dmic) interface can be digitally muted using the adcl_mute or adcr_mute bits. both channels are muted simultaneously when the adc_muteall bit is set. register address bit label default description r25 (19h) adc control 1 8 adc_muteall 1 adc digital mute for all channels 0 = disable mute 1 = enable mute on all channels r27 (1bh) adc digital vol 12 adc_vu 0 adc volume update writing a 1 to this bit wi ll cause left and right adc / dmic volume to be updated simultaneously 8 adcl_mute 0 adc / left dmic digital mute 0 = disable mute 1 = enable mute 7:0 adcl_vol [7:0] 1100_0000 (0db) adc / left dmic digital volume 0000_0000 = mute 0000_0001 = - 71.625db 0000_0010 = - 71.250db table 8 adc digital volume control
WM8944B rev 4. 3 29 table 9 adc digital volume range adcl_vol or adcr_vol volume (db) adcl_vol or adcr_vol volume (db) adcl_vol or adcr_vol volume (db) adcl_vol or adcr_vol volume (db) 0h mute 40h -48.000 80h -24.000 c0h 0.000 1h -71.625 41h -47.625 81h -23.625 c1h 0.375 2h -71.250 42h -47.250 82h -23.250 c2h 0.750 3h -70.875 43h -46.875 83h -22.875 c3h 1.125 4h -70.500 44h -46.500 84h -22.500 c4h 1.500 5h -70.125 45h -46.125 85h -22.125 c5h 1.875 6h -69.750 46h -45.750 86h -21.750 c6h 2.250 7h -69.375 47h -45.375 87h -21.375 c7h 2.625 8h -69.000 48h -45.000 88h -21.000 c8h 3.000 9h -68.625 49h -44.625 89h -20.625 c9h 3.375 ah -68.250 4ah -44.250 8ah -20.250 cah 3.750 bh -67.875 4bh -43.875 8bh -19.875 cbh 4.125 ch -67.500 4ch -43.500 8ch -19.500 cch 4.500 dh -67.125 4dh -43.125 8dh -19.125 cdh 4.875 eh -66.750 4eh -42.750 8eh -18.750 ceh 5.250 fh -66.375 4fh -42.375 8fh -18.375 cfh 5.625 10h -66.000 50h -42.000 90h -18.000 d0h 6.000 11h -65.625 51h -41.625 91h -17.625 d1h 6.375 12h -65.250 52h -41.250 92h -17.250 d2h 6.750 13h -64.875 53h -40.875 93h -16.875 d3h 7.125 14h -64.500 54h -40.500 94h -16.500 d4h 7.500 15h -64.125 55h -40.125 95h -16.125 d5h 7.875 16h -63.750 56h -39.750 96h -15.750 d6h 8.250 17h -63.375 57h -39.375 97h -15.375 d7h 8.625 18h -63.000 58h -39.000 98h -15.000 d8h 9.000 19h -62.625 59h -38.625 99h -14.625 d9h 9.375 1ah -62.250 5ah -38.250 9ah -14.250 dah 9.750 1bh -61.875 5bh -37.875 9bh -13.875 dbh 10.125 1ch -61.500 5ch -37.500 9ch -13.500 dch 10.500 1dh -61.125 5dh -37.125 9dh -13.125 ddh 10.875 1eh -60.750 5eh -36.750 9eh -12.750 deh 11.250 1fh -60.375 5fh -36.375 9fh -12.375 dfh 11.625 20h -60.000 60h -36.000 a0h -12.000 e0h 12.000 21h -59.625 61h -35.625 a1h -11.625 e1h 12.375 22h -59.250 62h -35.250 a2h -11.250 e2h 12.750 23h -58.875 63h -34.875 a3h -10.875 e3h 13.125 24h -58.500 64h -34.500 a4h -10.500 e4h 13.500 25h -58.125 65h -34.125 a5h -10.125 e5h 13.875 26h -57.750 66h -33.750 a6h -9.750 e6h 14.250 27h -57.375 67h -33.375 a7h -9.375 e7h 14.625 28h -57.000 68h -33.000 a8h -9.000 e8h 15.000 29h -56.625 69h -32.625 a9h -8.625 e9h 15.375 2ah -56.250 6ah -32.250 aah -8.250 eah 15.750 2bh -55.875 6bh -31.875 abh -7.875 ebh 16.125 2ch -55.500 6ch -31.500 ach -7.500 ech 16.500 2dh -55.125 6dh -31.125 adh -7.125 edh 16.875 2eh -54.750 6eh -30.750 aeh -6.750 eeh 17.250 2fh -54.375 6fh -30.375 afh -6.375 efh 17.625 30h -54.000 70h -30.000 b0h -6.000 f0h 18.000 31h -53.625 71h -29.625 b1h -5.625 f1h 18.375 32h -53.250 72h -29.250 b2h -5.250 f2h 18.750 33h -52.875 73h -28.875 b3h -4.875 f3h 19.125 34h -52.500 74h -28.500 b4h -4.500 f4h 19.500 35h -52.125 75h -28.125 b5h -4.125 f5h 19.875 36h -51.750 76h -27.750 b6h -3.750 f6h 20.250 37h -51.375 77h -27.375 b7h -3.375 f7h 20.625 38h -51.000 78h -27.000 b8h -3.000 f8h 21.000 39h -50.625 79h -26.625 b9h -2.625 f9h 21.375 3ah -50.250 7ah -26.250 bah -2.250 fah 21.750 3bh -49.875 7bh -25.875 bbh -1.875 fbh 22.125 3ch -49.500 7ch -25.500 bch -1.500 fch 22.500 3dh -49.125 7dh -25.125 bdh -1.125 fdh 22.875 3eh -48.750 7eh -24.750 beh -0.750 feh 23.250 3fh -48.375 7fh -24.375 bfh -0.375 ffh 23.625
WM8944B 30 rev 4. 3 adc high pass filter a digital high- pa ss filter is enabled by default to the adc path to remove dc offsets. this filter can also be used to remove low frequency noise in handheld applications (e.g. wind noise, handling noise or mechanical vibration). the adc high pass filter is enabled by adc_hpf. note that this filter must always be set when the dynamic range controller (drc) is enabled. the drc will not function correctly if adc_hpf is not set. the filter operates in one of two modes, selected by adc_hpf_mode. the adc_hpf_sr register should b e set according to the selected adc sample rate. see clocking and sample rates for details of the adc sample rate. in hi-fi mode (adc_hpf_mode = 0), the high-pass filter is optimised for removing dc offsets without degrading the bass response and has a cut-off frequency of 3.5hz when the sample rate (fs) = 44.1khz. in application mode (adc_hpf_mode = 1), the hpf cut-off frequency is set using adc_hpf_cut. this mode is intended for voice communication; it is recommended to set the cut-off frequency below 300hz (e.g. adc_hpf_cut = 101 when fs = 8khz or fs = 16khz). register address bit label default description r26 (1ah) adc control 2 6 adc_hpf_mod e 0 adc digital hpf mode 0 = hi - fi mode (1 st order) 1 = application mode (2 nd order) 5:4 adc_hpf_sr [1:0] 10 adc digital hpf sample rate 00 = 8khz to 12khz 01 = 16khz to 24khz 10 = 32khz to 48khz 11 = reserved 3 :1 adc_hpf_cut [ 2:0 ] 0 00 adc digital high pass filter cutoff note that the cut - off frequency scales with sample rate. see table 11 for cut - off frequencies at all supported sample rates. 0 adc_hpf 1 adc digital high pass filter enable 0 = disabled 1 = enabled table 10 adc high-pass filter control registers sample frequency ( k hz ) cut - off frequency ( hz ) hi - fi mode application mode / a dc_hpf_cut[2:0] 000 001 010 011 100 101 110 111 8.000 3.0 80.5 100.5 129.0 160.5 200.5 256.5 320.5 400.5 11.025 4.5 111.0 138.5 177.5 221.0 276.5 353.0 442.0 551.5 12.000 4.5 120.5 151.0 19 3.0 240.5 300.5 384.5 481.0 600.5 16.000 3.0 80.0 101.0 129.0 161.0 200.5 256.5 321.0 401.0 22.050 4.5 110.5 139.0 177.5 221.5 276.0 353.5 442.0 552.5 24.000 4.5 120.5 151.5 193.5 241.5 300.5 385.0 481.5 601.0 32.000 2.5 80.0 101.5 129.0 160.5 200.0 25 7.5 320.0 401.0 44.100 3.5 110.0 139.5 177.5 221.0 275.5 355.0 441.0 552.5 48.000 4.0 119.5 152.0 193.0 240.5 300.0 386.5 480.0 601.0 table 11 adc high-pass filter cut-off frequencies filter response plots for the adc high-pass filter are shown in digital filter characteristics .
WM8944B rev 4. 3 31 dsp core dsp core is at the centre of the adc / dac / digital audio interface (i2s) blocks. it provides signal routing, and also implements a number of configurable signal processing functions. the signal processing functions are arranged in three blocks, as follows: ? signal enhancement 1 (se1) - low -pass / high-pass filter, 3d -stereo enhancement, 5 notch filters, generic direct form 1 filter. ? signal enhancement 2 (se2) C high pass filter, retune ? processing, 5- band equali zer. ? signal enhancement 3 (se3) - dynamic range control. note that, although the WM8944B is largely a mono device, it supports a stereo signal path from the digital microphone interface to the digital audio interface. in the default configuration, the analogue input/output paths are associated with the left channel of the digital audio interface. the dsp configuration modes and each of the signal enhancement blocks is described in the following sections. dsp configuration modes the d sp configuration mode is determined using the se_config register field; this configures the signal paths between the signal enhancement blocks and the adc, digital microphone, dac and digital audio interfaces. the supported dsp modes are illustrated in figure 11. figure 11 dsp configuration modes dac digital audio interface dacdat adcdat lrclk bclk adc (left) digital audio interface dacdat adcdat lrclk bclk adc (left) dac digital audio interface dacdat adcdat lrclk bclk adc (left) se2 (hpf, re-tune, 5-band eq) dac digital audio interface dacdat adcdat lrclk bclk adc (left) se2 (hpf, re-tune, 5-band eq) se3 (dynamic range control) dac dsp record mode dsp playback mode dsp general mode 1 dsp general mode 2 se1 (lpf/hpf, 5-notch, df1) se2 (hpf, re-tune, 5-band eq) se3 (dynamic range control) se1 (lpf/hpf, 3d surround, 5-notch, df1) se1 (lpf/hpf, 3d surround, 5-notch, df1) se3 (dynamic range control) se1 (lpf/hpf, 3d surround, 5-notch, df1) se2 (hpf, re-tune, 5-band eq) se3 (dynamic range control) digital mic interface (left + right) digital mic interface (left + right) digital mic interface (left + right) digital mic interface (left + right)
WM8944B 32 rev 4. 3 record mode enables the entire set of signal enhancement functions in the adc / digital microphone path. the direct dac path is also active, without any signal enhancement functions; this allows basic audio playback and digital beep generation. playback mode enables the entire set of dsp functions in the dac path. the direct adc / digital microphone path is also active, without any dsp functions; this allows basic audio record functions to the host system. register address bit label default description r64 (40h) se config selection 3:0 se_config [3:0] 0000 dsp configuration mode select 0000 = record mode 0001 = playback mode 0010 = ds p general mode 1 0011 = dsp general mode 2 table 12 dsp configuration mode select low -pass / high-pass filter (lpf/hpf) the low-pass / high-pass filter is part of the se1 block. this first-order filter can be configured to be high-pass, low-pass; it can also be bypassed. the cut-off frequency is programmable; the default setting is bypass (off ). the filters are enabled using the se1_lhpf_l_ena and se1_lhpf_r_ena register bits defined in table 13. the 3d enhancement coefficients are programmed in registers r65 to r67. for the derivation of these registers, refer to the configuration tools supplied with the WM8944B evaluation kit. example plots of the low-pass / high-pass filter response are shown in figure 12. figure 12 low -pass / high-pass filter responses 3d surround 5-notch filter df1 filter l/hpf signal enhancement block 1 (se1) 1klpf.res magnitude(db) 1khpf.res magnitude(db) 5klpf.res magnitude(db) 5khpf.res magnitude(db) 200lpf.res magnitude(db) 200hpf.res magnitude(db) 20 39.91 79.62 158.9 317 632.5 1.262k 2.518k 5.024k 10.02k 20k -27 -24 -21 -18 -15 -12 -9 -6 -3 0 3
WM8944B rev 4. 3 33 3d surround the 3d-stereo surround effect is part of the se1 block. this function uses time delays and controlled cross-talk mechanisms to adjust the depth or width of the stereo audio. the 3d-stereo surround effect includes programmable high-pass or low-pass filtering to limit the 3d effect to specific frequency bands if required. the structure of the 3d surround processing is illustrated in figure 13. figure 13 3d surround processing the 3d surround depth is programmable; the default setting is off. the 3d surround processing can also be configured to create a mono mix of the left and right channels in the adc path. note that the 3d surround processing can only be used with the stereo digital microphone in the adc path. the 3d enhancement is enabled on the left and right channels using the se1_3d_l_ena and se1_3d_r_ena register bits defined in table 13 . (note that these bits can be enabled independently of each other.) the 3d enhancement coefficients are programmed in registers r68 to r7 0. for the derivation of these registers, refer to the configuration tools supplied with the WM8944B evaluation kit. 3d surround 5-notch filter df1 filter l/hpf signal enhancement block 1 (se1) hpf lpf bypass hpf lpf bypass z -n z -n + + l r forward_l forward_r cross_r cross_l
WM8944B 34 rev 4. 3 5-notch filter the 5-notch filter is part of the se1 block. this function allows up to 5 programmable frequency bands to be attenuated. the frequency and width of each notch is configurable; the depth of the attenuation may also be adjusted. the default setting is bypass (off). the notch filters are enabled on the left and right channels using the se1_notch_l_en a and se1_notch_r_ena register bits defined in table 13 . note that, although the 5-notch filter can be enabled on the left/right channels independently, the parameters that define the notch filters apply equally to the left and right channels, when enabled. the notch filter coefficients are programmed in registers r72 to r91. for the derivation of these registers, refer to the configuration tools supplied with the WM8944B evaluation kit. note that the notch filters should not be configured for centre-frequencies below 120hz. to apply filtering at low frequencies, the se1 high pass filter should be used. typical applications for the notch filters are filtering of fixed-frequency noise or resonances; these might arise from a motor (eg. dsc zoom lens motor) or from characteristics of the application housing. example plots of the notch filter response are shown in figure 14. 1khz notch, bandwidth 1khz, depth 0% to 100% in 2 0% steps 1khz notch, 100% depth, b andwidth 100hz, 500hz, 1khz, 5khz, 10khz 6 notches, bandwidth fcentre/2, depth 100% figure 14 notch filter responses 3d surround 5-notch filter df1 filter l/hpf signal enhancement block 1 (se1) notch response - slave mode - fc = 1 khz , fb = 1 khz depth 0 to 100 % - 100 t notch response - slave mode - fc = 1 khz , fb = 100 , 500 , 1 k , 5 k , 10 khz - depth = 100 % - 100 t notch response - slave mode - fc = 200 , 500 , 1 k , 2 k , 5 k , 10 khz , fb = fc / 2 , depth 100 % - 100 t
WM8944B rev 4. 3 35 df1 filter the df1 filter is part of the se1 block. this provides a direct-form 1 standard filter, as illustrated in figure 15 . the default coefficients give a transparent filter response. figure 15 direct-form 1 standard filter structure the df1 response is defined by the following equations: the df1 filters are enabled using the se1_df1_l_ena and se1_df1_r_ena registers bit defined in table 13. the df1 filter coefficients are programmed in registers r92 to r98 . for the derivation of these registers, refer to the configuration tools supplied with the WM8944B evaluation kit. the df1 filter can be used to implement very complex response patterns, with specific phase and gain responses at different frequencies. typical applications of this type of filter include the application of refinements or compensations to other user-selected filters. hpf the high pass filter (hpf) is part of the se2 block. the hpf cut-off frequency is fixed at 3.7hz , suitable for removing dc offsets in the record or playback path. the filters are enabled using the se2_hpf_l_ena and se2_hpf_r_ena register bits defined in table 14. 3d surround 5-notch filter df1 filter l/hpf signal enhancement block 1 (se1) + + z -1 z -1 c1 c2 c3 y x 1 3 1 21 3 2 1 1 ]1[]1[][][ ? ? ? ? ?? ????? zc zcc x y h nycnxcnxcny retune tm 5-band eq signal enhancement block 2 (se2) hpf
WM8944B 36 rev 4. 3 retune filter the retune ? filter is part of the se2 block. this is a very advanced feature that is intended to perform frequency linearization according to the particular needs of the application microphone, loudspeaker or housing. the retune algorithms can provide acoustic equalisation and selective phase (delay) control of specific frequency bands. the retune ? filters are enabled using the se2_retune_l_ena and se2_retune_r_ena register bits defined in table 14. the retune? filter coefficients are programmed in registers r101 to r132. for the derivation of the other retune configuration parameters, the wisce? software must be used to analyse the requirements of the application. (refer to wisce ? for further information.) if desired, one or more sets of register coefficients might be derived for different operating scenarios, and these may be recalled and written to the codec registers as required in the target application. the retune configuration procedure involves the generation and analysis of test signals as outlined below. to determine the characteristics of the microphone in an application, a test signal is applied to a loudspeaker that is in the acoustic path to the microphone. the received signal through the application microphone is analysed and compared with the received signal from a reference microphone in order to determine the characteristics of the application microphone. to determine the characteristics of the loudspeaker in an application, a test signal is applied to the target application. a reference microphone is positioned in the normal acoustic path of the loudspeaker, and the received signal is analysed to determine how accurately the loudspeaker has reproduced the test signal. 5-band eq the 5-band eq is part of the se2 block . this function allows 5 frequency bands to be controlled. the upper and lower frequency bands are controlled by low-pass and high-pass filters respectively. the middle three frequency bands are notch filters. the cut-off / centre frequency of each filter is programmable, and up to 12db gain or attenuation can be selected in each case. the 5-band eq is enabled using the se2_5beq_l_ena register bit defined in table 14. the 5-band eq coefficients are programmed in registers r132 to r175 . for the derivation of these registers, refer to the wisce tm software. typical applications of the 5-band eq include the selection of user-preferences for different music types, such as rock, dance or classical eq profiles. note that when the right channel 5beq filter is disabled the gains for each of the frequency bands must be set to 0db. retune tm 5-band eq signal enhancement block 2 (se2) hpf retune tm 5-band eq signal enhancement block 2 (se2) hpf
WM8944B rev 4. 3 37 dynamic range control (drc) the dynamic range control (drc) forms the se3 block. the drc provides a range of compression, limiting and noise gate functions to support optimum configuration for recording or playback modes. the drc is configured using the control fields in registers r29 to r35 - see dynamic range control. signal enhancement register contro ls the se1 enable bits are described in table 13 . note that other control fields must also be determined and written to the WM8944B using wisce? or other tools. the registers described below only allow the sub-blocks of se1 to be enabled or disabled. note that it is not recommended to access these control fields unless appropriate values have been written to the associated bits in registers r65 to r95. register address bit label default description r65 (41h) se1_lhpf_c onfig 1 se1_lhpf_r_e na 0 se1 right channel low - pass / high - pass filter enable 0 = disabled 1 = enabled 0 se1_lhpf_l_e na 0 se1 left channel low - pass / high - pass filter enable 0 = disabled 1 = enabled r68 (41h) se1_3d_con fig 1 se1_3d_r_ena 0 se1 right channel 3d stereo enhancement enable 0 = disabled 1 = enabled 0 se1_3d_l_ena 0 se1 left channel 3d stereo enhancement enable 0 = disabled 1 = enabled r71 (47h) se1_notch_ config 1 se1_notch_r _ena 0 se1 right channel notch filters enable 0 = disabl ed 1 = enabled 0 se1_notch_l_ ena 0 se1 left channel notch filters enable 0 = disabled 1 = enabled r92 (5ch) se1_df1_co nfig 1 se1_df1_r_en a 0 se1 right channel df1 filter enable 0 = disabled 1 = enabled 0 se1_df1_l_en a 0 se1 left channel df1 filter ena ble 0 = disabled 1 = enabled table 13 signal enhancement block 1 (se1) drc signal enhancement block 3 (se3)
WM8944B 38 rev 4. 3 the se2 enable bits are described in table 14 . note that (with the exception of the se2 hpf) other control fields must also be determined and written to the WM8944B using wisce? or other tools. the registers described below only allow the sub-blocks of se2 to be enabled or disabled. note that it is not recommended to access these control fields unless appropriate values have been wri tten to the associated bits in registers r99 to r175. register address bit label default description r99 (63h) se2_hpf_co nfig 1 se2_hpf_r_e na 0 se2 right channel high - pass filter enable 0 = disabled 1 = enabled 0 se2_hpf_l_en a 0 se2 left channel high - p ass filter enable 0 = disabled 1 = enabled r100 (64h) se2_retune _config 1 se2_retune_ r_ena 0 se2 right channel retune filter enable 0 = disabled 1 = enabled 0 se2_retune_ l_ena 0 se2 left channel retune filter enable 0 = disabled 1 = enabled r133 (85h) se2_5beq_c onfig 0 se2_5beq_l_e na 0 se2 left channel 5 - band eq enable 0 = disabled 1 = enabled table 14 signal enhancement block 2 (se2) the register controls for signal enhancement block se3 are defined in the dynamic range control (drc) section. dynamic range control (drc) the dynamic range controller (drc) is a circuit which can be enabled in the digital playback or digital record path of the WM8944B, depending upon the selected dsp mode. the function of the drc is to adjust the signal gain in conditions where the input amplitude is unknown or varies over a wide range, e.g. when recording from microphones built into a handheld system. the drc can apply compression and automatic level control to the si gnal path. it incorporates anti - clip and quick release features for handling transients in order to improve intelligibility in the presence of loud impulsive noises. the drc also incorporates a noise gate function, which provides additional attenuation of very low- level input signals. this means that the signal path is quiet when no signal is present, giving an improvement in background noise level under these conditions. the drc is enabled as described in table 15 . the audio signal path controlled by the drc depends upon the selected dsp configuration mode - see dsp core for details. if the drc is used in the record path then to remove any dc offset from the input signal the adc high pass filter must be enabled. the adc hpf is enabled when adc_hpf = 1. this is the default condition. the drc will not function correctly if there is any dc offset..
WM8944B rev 4. 3 39 register address bit label default description r29 (1dh) drc control 1 7 drc_ena 0 drc e nable 0 = disabled 1 = e nabled table 15 drc enable drc compression / expansion / limiting the drc supports two different compression regions, separated by a knee at a specific input amplitude. in the region above the knee, the compression slope drc_hi_comp applies; in the region below the knee, the compression slope drc_lo_comp applies. the drc also supports a noise gate region, where low-level input signals are heavily attenuated. this function can be enabled or disabled according to the application requirements. the drc response in this region is defined by the expansion slope drc_ng_exp. for additional attenuation of signals in the noise gate region, an additional knee can be defined (shown as k nee2 in figure 16 ). when this knee is enabled, this introduces an infinitely steep drop- off in the drc response pattern between the drc_lo_comp and drc_ng_exp regions. the overall drc compression characteristic in steady state (i.e. where the input amplitude is near - constant) is illustrated in figure 16. figure 16 drc response characteristic the slope of the drc response is determined by register fields drc_hi_comp and drc_lo_comp. a slope of 1 indicates constant gain in this region. a slope less than 1 represents compression (i.e. a change in input amplitude produces only a smaller change in output amplitude). a slope of 0 indicates that the target output amplitude is the same across a range of input amplitudes; this is infinite compression. when the noise gate is enabled, the drc response in this region is determined by the drc_ng_exp register. a slope of 1 indicates constant gain in this region. a slope greater than 1 represents expansion (ie. a change in input amplitude produces a larger change in output amplitude). when the drc_knee2_op knee is enabled ( k nee2 in figure 16 ), this introduces the vertical line in the response pattern illustrated, resulting in infinitely steep attenuation at this point in the response. drc_knee_ip (y0) 0db drc_hi_comp drc_lo_comp drc input amplitude (db) drc output amplitude (db) drc_knee_op knee1 knee2 drc_knee2_ip drc_ng_exp drc_knee2_op
WM8944B 40 rev 4. 3 the drc parameters are listed in table 16 . ref parameter description 1 drc_knee_ip input level at knee1 (db) 2 drc_knee_op output level at knee1 (db) 3 d rc_hi_comp compression ratio above knee1 4 drc_lo_comp compression ratio below knee1 5 drc_knee2_ip input level at knee2 (db) 6 drc_ng_exp expansion ratio below knee2 7 drc_knee2_op output level at knee2 (db) table 16 drc resp onse parameters the noise gate is enabled when the drc_ng_ena register is set. when the noise gate is not enabled, parameters 5, 6, 7 above are ignored, and the drc_lo_comp slope applies to all input signal levels below knee1. the drc_knee2_op knee is enabled when the drc_knee2_op_ena register is set. when this bit is not set, then parameter 7 above is ignored, and the knee2 position always coincides with the low end of the drc_lo_comp region. the k nee1 point in figure 16 is determined by register fields drc_knee_ip and drc_ knee_op. parameter y0, the output level for a 0db input, is not specified directly, but can be calculated from the other parameters, using the equation: the drc compression / expansion / limiting parameters are defined in table 17. register address bit label default description r29 (1dh) drc control 1 8 drc_ng_ena 0 drc noise gate enable 0 = disabled 1 = enabled r32 (20h) drc control 4 1 2:8 drc_knee2_ip 000000 input signal level at the noise gate threshold nee2. ( nee. ( y0 = drc_knee_op C (drc_knee_ip * drc_hi_comp)
WM8944B rev 4. 3 41 register address bit label default description r33 (21h) drc c ontrol 5 13 drc_knee2_op_ ena 0 drc_knee2_op enable 0 = disabled 1 = enabled 12:8 drc_knee2_op 00000 output signal at the noise gate threshold k nee2. ( k nee. ( table 17 drc control registers
WM8944B 42 rev 4. 3 knee input level (drc_knee_ip) knee output level (drc_knee_op) knee2 input level (drc_knee2_ip) knee2 output level (drc_knee2_op) r32[7:2] level r32[7:2] level r33[7:3] level r32[12:8] level r33[12:8] level 00h 0.00 20h - 24.00 00h 0.00 00h - 36.00 00h - 30.00 01h - 0.75 21h - 24.75 01h - 0.75 01h - 37.50 01h - 31.50 02h - 1.50 22h - 25.50 02h - 1.50 02h - 39.00 02h - 33.00 03h - 2.25 23h - 26.25 03h - 2.25 03h - 40.50 03h - 34.50 04h - 3.00 24h - 27.00 04h - 3.00 04h - 42.00 04h - 36.00 05h - 3.75 25h - 27.75 05h - 3.75 05h - 43.50 05h - 37.50 06h - 4.50 26h - 28.50 06h - 4.50 06h - 45.00 06h - 39.00 07h - 5.25 27h - 29.25 07h - 5.25 07h - 46.50 07h - 40.50 08h - 6.00 28h - 30.00 08h - 6.00 08h - 48.00 08h - 42.00 09h - 6.75 29h - 30.75 09h - 6.75 09h - 49.50 09h - 43.50 0ah - 7.50 2ah - 31.50 0ah - 7.50 0ah - 51.00 0ah - 45.00 0bh - 8.25 2bh - 32.25 0bh - 8.25 0bh - 52.50 0bh - 46.50 0ch - 9.00 2ch - 33.00 0ch - 9.00 0ch - 54.00 0ch - 48.00 0dh - 9.75 2dh - 33.75 0dh - 9.75 0dh - 55.50 0dh - 49.50 0eh - 10.50 2eh - 34.50 0eh - 10.50 0eh - 57.00 0eh - 51.00 0fh - 11.25 2fh - 35.25 0fh - 11.25 0fh - 58.50 0fh - 52.50 10h - 12.00 30h - 36.00 10h - 12.00 10h - 60.00 10h - 54.00 11h - 12.75 31h - 36.75 11h - 12.75 11h - 61.50 11h - 55.50 12h - 13.50 32h - 37.50 12h - 13.50 12h - 63.00 12h - 57.00 13h - 14.25 33h - 38.25 13h - 14.25 13h - 64.50 13h - 58.50 14h - 15.00 34h - 39.00 14h - 15.00 14h - 66.00 14h - 60.00 15h - 15.75 35h - 39.75 15h - 15.75 15h - 67.50 15h - 61.50 16h - 16.50 36h - 40.50 16h - 16.50 16h - 69.00 16h - 63.00 17h - 17.25 37h - 41.25 17h - 17.25 17h - 70.50 17h - 64.50 18h - 18.00 38h - 42.00 1 8h - 18.00 18h - 72.00 18h - 66.00 19h - 18.75 39h - 42.75 19h - 18.75 19h - 73.50 19h - 67.50 1ah - 19.50 3ah - 43.50 1ah - 19.50 1ah - 75.00 1ah - 69.00 1bh - 20.25 3bh - 44.25 1bh - 20.25 1bh - 76.50 1bh - 70.50 1ch - 21.00 3ch - 45.00 1ch - 21.00 1ch - 78.00 1ch - 72.00 1dh - 21.75 3dh reserved 1dh - 21.75 1dh - 79.50 1dh - 73.50 1eh - 22.50 3eh reserved 1eh - 22.50 1eh - 81.00 1eh - 75.00 1fh - 23.25 3fh reserved 1fh reserved 1fh - 82.50 1fh - 76.50 table 18 drc digital gain range
WM8944B rev 4. 3 43 gain limits the minimum and maximum gain applied by the drc is set by register fields drc_mingain, drc_maxgain and drc_ng_mingain. these limits can be used to alter the drc response from that illustrated in figure 16. if the range between maximum and minimum gain is reduced, then the extent of the dynamic range control is reduced. the minimum gain in the compression regions of the drc response is set by drc_mingain. the mimimum gain in the noise gate region is set by drc_ng_mingain. the minimum gain limit prevents excessive attenuation of the signal path. the maximum gain limit set by drc_maxgain prevents quiet signals (or silence) from being excessively amplified. register address bit label default description r30 (1eh) drc control 2 1 2:9 drc_ng_ming ain [3:0] 0110 minimum gain the drc can use to attenuate audio signals when the noise gate is active. 0000 = - 36db 0001 = - 30db 0010 = - 24db 0011 = - 18db 0100 = - 12db 0101 = - 6db 0110 = 0db 0111 = 6db 1000 = 12db 1001 = 18db 1010 = 24db 1 011 = 30db 1100 = 36db 1101 to 1111 = reserved 4:2 drc_mingain [2:0] 001 minimum gain the drc can use to attenuate audio signals 000 = 0db 001 = - 12db (default) 010 = - 18db 011 = - 24db 100 = - 36db 101 = reserved 11x = reserved 1:0 drc_maxgain [1:0] 01 maximum gain the drc can use to boost audio signals (db) 00 = 12db 01 = 18db 10 = 24db 11 = 36db table 19 drc gain limits
WM8944B 44 rev 4. 3 gain readback the gain applied by the drc can be read from the drc_gain register. this is a 16-bit, fixed-point value, which expresses the drc gain as a voltage multiplier. drc_gain is coded as a fixed-point quantity, with an msb weighting of 64 . the first 7 bits represent the integer portion; the remaining bits represent the fractional portion. if desired, the value of this field may be interpreted by treating drc_gain as an integer value, and dividing the result by 512, as illustrated in the following examples: drc_gain = 05d4 (hex) = 1380 (decimal) divide by 512 gives 2.914 voltage gain, or 4.645db drc_gain = 0100 (hex) = 256 (decimal) divide by 512 gives 0.5 voltage gain, or - 3.01db the drc_gain register is defined in table 20. register address bit label default description r36 (24h) drc status (read only) 15:0 drc_gain [15:0] dr c gain value (read only). this is the drc gain, expressed as a voltage multiplier. fixed point coding, msb = 64. the first 7 bits are the integer portion; the remaining bits are the fractional part. table 20 drc gain readback
WM8944B rev 4. 3 45 dynamic characteristics the dynamic behaviour determines how quickly the drc responds to changing signal levels. note that the drc responds to the peak signal amplitude over a period of time. the drc_atk determines how quickly the drc gain decreases when the signal amplitude is high. the drc_dcy determines how quickly the drc gain increases when the signal amplitude is low. these register fields are described in table 21 . note that the register defaults are suitable for general purpose microphone use. register address bit label default description r31 (1fh) drc control 3 7:4 drc_atk [3:0] 0100 a ttack rate relative to the input signal (seconds/6db) 0000 = reserved 0001 = 181us 0010 = 363us 0011 = 726us 0100 = 1.45ms 0101 = 2.9ms 0110 = 5.8ms 0111 = 11.6ms 1000 = 23.2ms 1001 = 46.4ms 1010 = 92.8ms 1011 = 185.6ms 1100 - 1111 = reserved 3:0 drc_dcy [3:0] 0010 d ecay rate relative to the input signal (seconds/6db) 0000 = 186ms 0001 = 372ms 0010 = 743ms 0011 = 1.49s 0100 = 2.97s 0101 = 5.94s 0110 = 11.89s 0111 = 23.78s 1000 = 47.56s 1001 - 1111 = reserved table 21 drc time constants under the following conditions, it is possible to predict the attack times with an input sine wave: decay rate is set at least 8 times the attack rate. attack time * input frequency > 1 to estimate the attack time for 10%-90%: attack time = register value * 2.24 for example, if drc_atk = 1.45ms/6db, then the attack time (10%-90%) = 1.45ms * 2.24 = 3.25ms. the decay time for 10%-90% can be estimated using the graph in figure 17.
WM8944B 46 rev 4. 3 figure 17 decay time vs register value decay rate the decay rate register value read from the horizontal axis and the decay time (10%-90%) read fr om the vertical axis. for example, if drc drc_dcy = 743ms/6db, then the estimate decay time (10%-90%) taken from the graph is 1.0s. anti-clip control the drc includes an anti-clip feature to avoid signal clipping when the input amplitude rises very quickly. this feature uses a feed-forward technique for early detection of a rising signal level. signal clipping is avoided by dynamically increasing the gain attack rate when required. the anti-clip feature is enabled using the drc_anticlip bit. note that the feed -forward processing increases the latency in the input signal path. the drc anti- clip control is described in table 22. register address bit label default description r29 (1dh) drc control 1 1 drc_anticli p 1 d rc a nti - clip enable 0 = disabled 1 = enabled table 22 drc anti-clip control note that the anti-clip feature operates entirely in the digital domain. it cannot be used to prevent signal clipping in the analogue domain nor in the source signal. analogue clipping can only be prevented by reducing the analogue signal gain or by adjusting the source signal. note that the anti-clip and quick release features should not be used at the same time.
WM8944B rev 4. 3 47 quick-release control the drc includes a quick-release feature to handle short transient peaks that are not related to the intended source signal. for example, in handheld microphone recording, transient signal peaks sometimes occur due to user handling, key presses or accidental tapping against the microphone. the quick release feature ensures that these transients do not cause the intended signal to be masked by the longer time constants of drc_dc y. the quick-release feature is enabled by setting the drc_qr bit. when this bit is enabled, the drc measures the crest factor (peak to rms ratio) of the input signal. a high crest factor is indicative of a transient peak that may not be related to the intended source signal. if the crest factor exceeds the level set by drc_qr_thr, then the normal decay rate (drc_dcy) is ignored and a faster decay rate (drc_qr_dcy) is used instead. the drc quick-release control bits are described in table 23. register address bit label default description r29 (1dh) drc control 1 2 drc_qr 1 drc qu ick - release enable 0 = disabled 1 = enabled r34 (22h) drc control 6 3:2 drc_qr_thr [1:0] 00 drc q uick - release threshold (crest factor in db) 00 = 12db 01 = 18db 10 = 24db 11 = 30db 1:0 drc_qr_dcy [1:0] 00 drc q uick - release decay rate (seconds/6db) 00 = 0.725ms 01 = 1.45ms 10 = 5.8ms 11 = reserved table 23 drc quick- release control note that the anti-clip and quick release features should not be used at the same time. drc initial condition the drc can be set up to a defined initial condition based on the expected signal level when the drc is enabled. this can be set using the drc_init bits in register r35 (23h) bits 4 to 0. note: this does not set the initial gain of the drc. it sets the expected signal level of the drc input sig nal when the drc is enabled. register address bit label default description r35 (23h) drc control 7 4:0 drc_init 00000 initial value at drc startup 00000 = 0db 00001 = - 3.75db ( table 24 drc initial condition
WM8944B 48 rev 4. 3 digital- to -analogue converter ( dac) the WM8944B dac receives digital input data from the digital audio interface. (note that, depending on the dsp configuration mode, the digital input may first be processed and filtered in the dsp core. ) th e digital audio data is converted to an oversampled bit-stream in the on-chip, true 24-bit digital interpolation filter. the bit-stream data enters the multi-bit, sigma-delta dac, which converts it to high quality analogue audio. the analogue output from the dac can then be mixed with other analogue inputs before being sent to the analogue output pins (see output signal path). the dac is enabled by the dac_ena register bit. register address bit label default description r3 (03h) power management 2 0 dac_ ena 0 dac enable 0 = disabled 1 = enabled dac_ena must be set to 1 when processing data from the dac or digital beep generator. table 25 dac enable control dac digital volume control the output of the dac can be digitally amplified or attenuated over a range from - 71.625db to + 23 .625db in 0.375db steps. the volume can be controlled using dac_vol. the dac volume is part of the dac digital filters block. the gain for a given eight-bit code x is given by: 0.375 ? (x -192) db for 1 ? x ? 255 ; mute for x = 0 the output of the dac can be digitally muted using the dac_mute bit. a digital soft-mute feature is provided in order to avoid sudden glitches in the analogue signal. when dac_vol_ramp is enabled, then all mute, un-mute or volume change commands are implemented as a gradual volume change in the digital domain. the rate at which the volume ramps up is half of the sample freq (fs/2). the dac_vol_ramp register field is described in table 26. register address bit label default description r22 (16h) dac control 2 4 dac_vol_ramp 1 dac volume ramp control 0 = disabled 1 = enabled r23 (17h) dac digital vol 8 dac_mute 1 dac digital mute 0 = disable mute 1 = enable mute 7:0 dac_vol [7:0] 1100_0000 (0db) dac digi tal volume 0000_0000 = mute 0000_0001 = - 71.625db 0000_0010 = - 71.250db table 26 dac digital volume control
WM8944B rev 4. 3 49 table 27 dac digital volume range dac_vol volume (db) dac_vol volume (db) dac_vol volume (db) dac_vol volume (db) 0h mute 40h -48.000 80h -24.000 c0h 0.000 1h -71.625 41h -47.625 81h -23.625 c1h 0.375 2h -71.250 42h -47.250 82h -23.250 c2h 0.750 3h -70.875 43h -46.875 83h -22.875 c3h 1.125 4h -70.500 44h -46.500 84h -22.500 c4h 1.500 5h -70.125 45h -46.125 85h -22.125 c5h 1.875 6h -69.750 46h -45.750 86h -21.750 c6h 2.250 7h -69.375 47h -45.375 87h -21.375 c7h 2.625 8h -69.000 48h -45.000 88h -21.000 c8h 3.000 9h -68.625 49h -44.625 89h -20.625 c9h 3.375 ah -68.250 4ah -44.250 8ah -20.250 cah 3.750 bh -67.875 4bh -43.875 8bh -19.875 cbh 4.125 ch -67.500 4ch -43.500 8ch -19.500 cch 4.500 dh -67.125 4dh -43.125 8dh -19.125 cdh 4.875 eh -66.750 4eh -42.750 8eh -18.750 ceh 5.250 fh -66.375 4fh -42.375 8fh -18.375 cfh 5.625 10h -66.000 50h -42.000 90h -18.000 d0h 6.000 11h -65.625 51h -41.625 91h -17.625 d1h 6.375 12h -65.250 52h -41.250 92h -17.250 d2h 6.750 13h -64.875 53h -40.875 93h -16.875 d3h 7.125 14h -64.500 54h -40.500 94h -16.500 d4h 7.500 15h -64.125 55h -40.125 95h -16.125 d5h 7.875 16h -63.750 56h -39.750 96h -15.750 d6h 8.250 17h -63.375 57h -39.375 97h -15.375 d7h 8.625 18h -63.000 58h -39.000 98h -15.000 d8h 9.000 19h -62.625 59h -38.625 99h -14.625 d9h 9.375 1ah -62.250 5ah -38.250 9ah -14.250 dah 9.750 1bh -61.875 5bh -37.875 9bh -13.875 dbh 10.125 1ch -61.500 5ch -37.500 9ch -13.500 dch 10.500 1dh -61.125 5dh -37.125 9dh -13.125 ddh 10.875 1eh -60.750 5eh -36.750 9eh -12.750 deh 11.250 1fh -60.375 5fh -36.375 9fh -12.375 dfh 11.625 20h -60.000 60h -36.000 a0h -12.000 e0h 12.000 21h -59.625 61h -35.625 a1h -11.625 e1h 12.375 22h -59.250 62h -35.250 a2h -11.250 e2h 12.750 23h -58.875 63h -34.875 a3h -10.875 e3h 13.125 24h -58.500 64h -34.500 a4h -10.500 e4h 13.500 25h -58.125 65h -34.125 a5h -10.125 e5h 13.875 26h -57.750 66h -33.750 a6h -9.750 e6h 14.250 27h -57.375 67h -33.375 a7h -9.375 e7h 14.625 28h -57.000 68h -33.000 a8h -9.000 e8h 15.000 29h -56.625 69h -32.625 a9h -8.625 e9h 15.375 2ah -56.250 6ah -32.250 aah -8.250 eah 15.750 2bh -55.875 6bh -31.875 abh -7.875 ebh 16.125 2ch -55.500 6ch -31.500 ach -7.500 ech 16.500 2dh -55.125 6dh -31.125 adh -7.125 edh 16.875 2eh -54.750 6eh -30.750 aeh -6.750 eeh 17.250 2fh -54.375 6fh -30.375 afh -6.375 efh 17.625 30h -54.000 70h -30.000 b0h -6.000 f0h 18.000 31h -53.625 71h -29.625 b1h -5.625 f1h 18.375 32h -53.250 72h -29.250 b2h -5.250 f2h 18.750 33h -52.875 73h -28.875 b3h -4.875 f3h 19.125 34h -52.500 74h -28.500 b4h -4.500 f4h 19.500 35h -52.125 75h -28.125 b5h -4.125 f5h 19.875 36h -51.750 76h -27.750 b6h -3.750 f6h 20.250 37h -51.375 77h -27.375 b7h -3.375 f7h 20.625 38h -51.000 78h -27.000 b8h -3.000 f8h 21.000 39h -50.625 79h -26.625 b9h -2.625 f9h 21.375 3ah -50.250 7ah -26.250 bah -2.250 fah 21.750 3bh -49.875 7bh -25.875 bbh -1.875 fbh 22.125 3ch -49.500 7ch -25.500 bch -1.500 fch 22.500 3dh -49.125 7dh -25.125 bdh -1.125 fdh 22.875 3eh -48.750 7eh -24.750 beh -0.750 feh 23.250 3fh -48.375 7fh -24.375 bfh -0.375 ffh 23.625
WM8944B 50 rev 4. 3 dac auto-mute the dac digital mute and volume controls are described earlier in table 26. the dac also incorporates an analogue auto-mute, which is enabled by setting dac_automute. when the auto-mute is enabled, and a series of 1024 consecutive zero-samples is detected, the dac output is muted in order to attenuate noise that might be present in output signal path. the dac resumes normal operation as soon as digital audio data is detected. register address bit label default description r21 (15h) dac control 1 4 dac_automut e 1 dac auto - m ute c ontrol 0 = d isabled 1 = e nabled table 28 dac auto mute note: the dac_automute bit should not be set when the beep generator is used. dac sloping stopband filter two dac filter types are available, selected by the register bit dac_sb_flt. when operating at lower sample rates (e.g. during voice communication) it is recommended that the sloping stopband filter type is selected (dac_sb_flt=1) to reduce out- of -band noise which can be audible at low dac sample rates. see digital filter characteristics for details of dac filter characteristics. register address bit label default description r 22 (16h) dac control 2 0 dac_sb_flt 0 selects dac filter characteristics 0 = normal mode 1 = sloping stopband mode table 29 dac sloping stopband filter
WM8944B rev 4. 3 51 digital beep generat or the WM8944B provides a digital signal generator which can be used to inject an audio tone (beep) into the dac signal path. the output of the beep generator is digitally mixed with the dac outputs, after the dac digital volume. the beep is enabled using beep_ena. the beep function creates an approximation of a sine wave. the audio frequency is set using beep_rate. the beep volume is set using beep_gain. note that the volume of the digital beep generator is not affected by the dac volume or dac mute controls but the dac_ena bit must be set. the dac_automute bit should not be set when the beep generator is used. the digital beep generator control fields are described in table 30. register address bit label default description r37 (25h) beep control 1 6:3 beep_gain [3:0] 0000 digital beep volume control 0000 = mute 0001 = - 83db 0010 = - 77db (6db steps) table 30 digital beep generator output signal path the WM8944B provides a line output mixer and a speaker output mixer. multiple inputs to each mixer provide a high degree of flexibility to route different signal paths to each of the analogue outputs. the dac output can be routed to the mixers either directly or in inverted phase. this provides additional capability to generate differential (btl) output signals. the analogue inputs aux and in1 can be configured as a differential signal path to the mixers, bypassing the input pga. this configuration can be used to minimise power consumption. the analogue inputs aux and in1 can be routed directly to the speaker o utput s, bypassing the speaker pga and mixers. this can be used to provide a fixed- gain signal path for a pc beep or similar application. the output signal paths and associated control registers are illustrated in figure 18. note that the speaker outputs are intended to drive a mono headset or speaker (in btl configuration). they are not designed to drive stereo speakers.
WM8944B 52 rev 4. 3 figure 18 output signal paths in1 aux bypass dac digital filters dac mixspk mixout spkpga + + spkoutp spkoutn lineout -1 spkoutp spkoutn digital beep generator WM8944B dac_vol[7:0] dac_sb_flt spk_vol aux_to_spkp spkn_spkvdd_ena spkn_op_ena dac_ena beep_gain[3:0] beep_rate[1:0] beep_ena in1_to_spkn out_ena spk_mix_ena spk_pga_ena pga_to_spkp pga_to_spkn byp_to_out mdac_to_out dac_to_out in1_to_out aux_to_out byp_to_pga mdac_to_pga dac_to_pga in1_to_pga aux_to_pga line_mute spk_mix_mute spkn_op_mute spkp_spkvdd_ena spkp_op_ena spkp_op_mute -1 + + auxdiff_to_out auxdiff_to_pga + - + -
WM8944B rev 4. 3 53 output signal paths enable each analogue output pin can be independently enabled or disabled using the register bits described in table 31 . the speaker pga and mixers can also be controlled. register address bit label default description r3 (03h) power ma nagement 2 14 out_ena 0 lineout enable 0 = disabled 1 = enabled 12 spk _ pga_ena 0 speaker pga enable 0 = disabled 1 = enabled 11 spkn _spkvdd_ ena 0 spkoutn enable 0 = disabled 1 = enabled note that spkoutn is also controlled by spkn _op_ena. when powering down spkoutn , the spkn _spkvdd_ena bit should be reset first. 10 spk p _spkvdd_ ena 0 spkoutp enable 0 = disabled 1 = enabled note that spkoutp is also controlled by spkp _op_ena. when powering down spkoutp , the spkp _spkvdd_ena bit should be reset first 7 spkn_op_ena 0 spkoutn enable 0 = disabled 1 = enabled note that spkoutn is also controlled by spkn_spkvdd_ena. when powering up spkoutn, the spkn_op_ena bit should be enabled first. 6 spkp_op_ena 0 spkoutp enable 0 = disabled 1 = enabled note that spkout p is also controlled by spkp_spkvdd_ena. when powering up spkoutp, the spkp_op_ena bit should be enabled first 2 spk_mix_ena 0 speaker output mixer enable 0 = disabled 1 = enabled table 31 output signal paths enable to enable the output pga and mixers, the reference voltage vmid and the bias current must also be enabled. see reference voltages and master bias for details of the associated controls vmid_sel and bias_ena. note that the line output, speaker outputs , speaker pga mixer and speaker pga are all muted by default. the required signal paths must be un-muted using the control bits described in the respective tables below.
WM8944B 54 rev 4. 3 line output mixer control the line output mixer (outmix) controls are described in table 32. these allow any of the dac, inverted dac, in1, aux and adc bypass signals to be mixed. a differential aux/in1 signal can also be selected in the line output mixer . the output of the mixer can be muted using the line_mute bit. note that, when selecting the differential aux/in1 signal as an input to the line output mixer, the in1 pin provides the non-inverting path and the aux pin provides the inverting signal path. care should be taken when mixing more than one path to the line output mixer in order to avoid clipping. the gain of each input path is adjustable using a selectable -6db control in each path t o facilitate this. note that the attenuation control field dac_to_out_atten controls the dac and the inverted da c mixer paths to the line output mixer. note that the dac input level may also be controlled by the dac digital volume control - see digital to analogue converter (dac) for further details. register address bit label default description r42 (2ah) output ctrl 8 line_mute 1 lineout output mute 0 = disable mute 1 = enable mute r49 (31h) line mixer control 1 10 auxdiff_to_o ut 0 differential aux/in1 to line output mixer select 0 = disabled 1 = enabled 9 in1_to_out 0 in1 to line output mixer select 0 = disa bled 1 = enabled 6 byp_to_out 0 input pga (adc bypass) to line output mixer select 0 = disabled 1 = enabled 5 mdac_to_out 0 inverted dac to line output mixer select 0 = disabled 1 = enabled 3 dac_to_out 0 dac to line output mixer select 0 = disabled 1 = enabled 0 aux_to_out 0 aux to line output mixer select 0 = disabled 1 = enabled r51 (33h) line mixer control 2 10 auxdiff_to_o ut_atten 0 differential aux/in1 to line output mixer attenuation 0 = 0db 1 = - 6db attenuation 9 in1_to_out_at ten 0 in1 to line output mixer attenuation 0 = 0db 1 = - 6db attenuation 6 byp_to_out_a tten 0 input pga (adc bypass) to line output mixer attenuation 0 = 0db 1 = - 6db attenuation 3 dac_to_out_a tten 0 dac to line output mixer attenuation 0 = 0db 1 = - 6db attenuation
WM8944B rev 4. 3 55 register address bit label default description 0 aux_to_out_a tten 0 aux to line output mixer attenuation 0 = 0db 1 = - 6db attenuation table 32 line output mixer (mixout) control speaker pga mixer control the speaker pga mixer (mixspk) controls are described in table 33 . these allow any of the dac, inverted dac, in1, aux and adc bypass signals to be mixed. a differential aux/in1 signal can also be selected in the speaker pga mixer . the output of the speaker pga mixer can be muted using the spk_mix _m ute bit. note that, when selecting the differential aux/in1 signal as an input to the speaker pga mixer, the in1 pin provides the non-inverting path and the aux pin provides the inverting signal path. note that the output from the speaker pga mixer is also controlled by the speaker pga volume control and the speaker output control described in the following sections. care should be taken when enabling more than one path to the speaker pga mixer in order to avoid clipping. the gain of each input path is adjustable using a selectable -6db control in each path to facilitate this. note that the attenuation control field dac_to_pga_atten controls the dac and the inverted dac mixer paths to the speaker pga mixer. note that the dac input level may also be controlled by the dac digital volume control - see digital to analogue converter (dac) for further details. register address bit label default description r3 (03h) power management 1 4 spk_mix_mute 1 speaker pga mixer mute 0 = disable mute 1 = enable mute r43 ( 2bh) spk mixer control 1 10 auxdiff_to _ pg a 0 differential aux/in1 to speaker pga mixer select 0 = disabled 1 = enabled 9 in1_to_pga 0 in1 to speaker pga mixer select 0 = disabled 1 = enabled 6 byp_to_pga 0 input pga (adc bypass) to speaker pga mixer select 0 = disabled 1 = enabled 5 mdac_to_pga 0 inverted dac to speaker pga mixer select 0 = disabled 1 = enabled 3 dac_to_pga 0 dac to speaker pga mixer select 0 = disabled 1 = enabled 0 aux_to_pga 0 aux to speaker pga mixer select 0 = disabled 1 = enabled r45 (2dh) spk mixer control 3 10 auxdiff_to_pg a_atten 0 differential aux/in1 to speaker pga mixer attenuation 0 = 0db 1 = - 6db attenuation
WM8944B 56 rev 4. 3 register address bit label default description 9 in1_to_pga_at ten 0 in1 to speaker pga mixer attenuation 0 = 0db 1 = - 6db attenuation 6 byp_to_pga_a tte n 0 input pga (adc bypass) to speaker pga mixer attenuation 0 = 0db 1 = - 6db attenuation 3 dac_to_pga_a tten 0 dac to speaker pga mixer attenuation 0 = 0db 1 = - 6db attenuation 0 aux_to_pga_a tten 0 aux to speaker pga mixer attenuation 0 = 0db 1 = - 6db a ttenuation table 33 speaker pga mixer (mixspk) control speaker pga volume control the volume control of the speaker pga can be adjusted using the spk_vol register field as described in table 34 . the gain range is -57db to +6db in 1db steps. note that the output from the speaker pga volume control is an input to the speaker output control described in the following section. to prevent "zipper noise", a zero-cross function is provided on the speaker pga. when this feature is enabled, volume updates will not take place until a zero-crossing is detected. note that any dc offset in the dac data should be less than the peak data to ensure there are zero- crossings. the speaker pga volume control register fields are described in table 34. register address bit label default description r47 (2fh) spk volume ctrl 7 spk_zc 0 speaker pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 6 spk _pga_mute 1 speaker pga mute 0 = disable mute 1 = enable mute 5:0 spk_vol [5:0] 1 1 _ 1001 (0db) speaker pga volume 00_0000 = - 57db gain 00_0001 = - 56db table 34 speaker pga volume control
WM8944B rev 4. 3 57 pga gain setting volume (db) pga gain setting volume (db) 0 0h - 57 20h - 25 0 1h - 56 21h - 24 0 2h - 55 22h - 23 0 3h - 54 23h - 22 0 4h - 53 24h - 21 0 5h - 52 25h - 20 0 6h - 51 26h - 19 0 7h - 50 27h - 18 0 8h - 49 28h - 17 0 9h - 48 29h - 16 0 ah - 47 2ah - 15 0 bh - 46 2bh - 14 0 ch - 45 2ch - 13 0 dh - 44 2dh - 12 0 eh - 43 2eh - 11 0 fh - 42 2fh - 10 10h - 41 30h - 9 11h - 40 31h - 8 12h - 39 32h - 7 13h - 38 33h - 6 14h - 37 34h - 5 15h - 36 35h - 4 16h - 35 36h - 3 17h - 34 37h - 2 18h - 33 38h - 1 19h - 32 39h 0 1ah - 31 3ah +1 1bh - 30 3bh +2 1ch - 29 3ch +3 1dh - 28 3dh +4 1eh - 27 3eh +5 1fh - 26 3fh +6 table 35 speaker pga volume range
WM8944B 58 rev 4. 3 speaker output contr ol each speaker output has its own output mixer. this allows the output of the speaker pga to be enabled or disabled, and also allows the aux and in1 inputs to be routed directly to the speaker outputs. (aux can be routed to spkoutp; in1 can be routed to spkoutn, as illustr at ed in figure 18 . the two speaker outputs can be muted also, using spkn _op_mute and spkp _op_mute. as described above, the analogue inputs aux and in1 can be routed directly to the speaker outputs, bypassing the speaker pga and mixers. this can be used to provide a fixed-gain signal path that is unaffected by the speaker pga setting. this feature is intended for a pc beep or similar applications. care should be taken when enabling more than one path to the speaker output mixers in order to avoid clipping. the gain of each input path is adjustable using a selectable -6db control in each path to facilitate this. the speaker output control registers are described in table 36. register address bit label default description r3 (03h) power management 1 9 spkn _op_mute 1 spkoutn output mute 0 = disable mute 1 = enable mute 8 spkp _op_mute 1 spkoutp output mute 0 = disable mute 1 = enable mute r43 (2bh) spk mixer control 1 8 aux_to_spkp 0 aux to spkoutp select 0 = disabled 1 = enabled 7 pga _to_spkp 0 speaker pga mixer to spkoutp select 0 = disabled 1 = enabled r44 (2ch) spk mixer control2 9 in1_to_spkn 0 in1 to spkoutn select 0 = disabled 1 = enabled 7 pga_to_spkn 0 speaker pga mixer to spkoutn select 0 = disabled 1 = enabled r45 (2dh) s pk mixer control3 8 aux_to_spkp_ atten 0 aux to spkoutp attenuation 0 = 0db 1 = - 6db attenuation 7 pga_to_spkp_ atten 0 speaker pga mixer to spkoutp attenuation 0 = 0db 1 = - 6db attenuation r46 (2eh) spk mixer control4 9 in1_to_spkn _ atten 0 in1 to spkout n attenuation 0 = 0db 1 = - 6db attenuation 7 pga_to_spkn_ atten 0 speaker pga mixer to spkoutn attenuation 0 = 0db 1 = - 6db attenuation table 36 speaker output control
WM8944B rev 4. 3 59 analogue outputs the line output and speaker output pins are highly configurable and may be used in many different ways. the output mixers can be configured to generate single-ended or differential outputs. the class ab speaker output driver can deliver up to 400mw into an 8 ? speaker in btl mode. line output the line output lineout is the external connection to the mixout mixer . this is a single- ended output driver. note that single -ended line output can also be provided on spkoutp and spkoutn. speaker outputs the speaker outputs spkoutp and spkoutn are the external connections to the speaker output mixers. these outputs are intended for a mono speaker or headphone in btl configuration or for a twin mono line load. in a typical application, a btl output from the dac may be generated at the speaker outputs by routin g the speaker pga to the spkoutp and spkoutn pins. the analogue inputs aux and in1 may also be routed to the spkoutp and spkoutn outputs by enabling the respective signal path in each of the speaker output mixers. external components for line output in single-ended output configurations, dc blocking capacitors are required at the output pins (lineout, spkoutp and spkoutn ). see applications information for details of these components.
WM8944B 60 rev 4. 3 ldo regulator the WM8944B provides an internal ldo which provides a regulated voltage for use as an internal supply and reference, which can also be used to power external circuits. the ldo is enabled by setting the ldo_ena register bit. the ldo supply is drawn from the ldovdd pin; the ldo output is provided on the ldovout pin. the ldo requires a reference voltage and a bias source; these are configured as described below. the ldo bias source (master bias or start-up bias) is selected using bias_src. care is required during start-up to ensure that the selected bias is enabled; the master bias will not normally be available at initial start- up, and the start- up bias should be selected in the first instance. the ldo reference voltage can be selected using ldo_ref_sel; this allows selection of either the internal bandgap reference or one of the vmid resistor strings. when vmid is selected as the reference, then ldo_ref_sel_fast selects either the normal vmid reference or the fast-start vmid reference. care is required during start-up to ensure that the selected reference is enabled; the vmid references are enabled using vmid_ena and vmid_fast_start as described in table 40 and table 41 respectively.the internal bandgap reference is nominally 1.5v. note that this value is not trimmed and may vary significantly (+/-10%) between different devices. when using this reference, the internal bandgap reference must be enabled by setting the bg_ena register, as described in table 37 . the bandgap voltage can be adjusted using the bg_vsel register as described in table 39. the ldo output voltage is set using the ldo_vsel register, which sets the ratio of the output voltage to the ldo reference voltage. see table 38 for ldo output voltages. example1: how to generate an ldovout voltage of 3.0v from a 3.3v ldovdd supply voltage. if vmid is selected as the reference voltage for the ldo (ldo_ref_sel = 0) then the vmid voltage must be supplied from ldovdd (vmid_ref_sel = 0) and the vmid ratio set to 5/11 (vmid_ctrl = 0). this gives vmid = 1.5v. the default ldo_vsel gives ldovout = vref * 1.97 = 1.5v * 1.97 = 2.96v (see table 38 ). example2: generating an ldovout volt age of 2.4v from a 3.0v ldovdd supply. for maximum signal swing the vmid voltage should be half of the ldovout voltage. for ldovout of 2.4v the optimum vmid voltage is 1.2v. select the vmid source voltage as ldovout (vmid_ref_sel = 1) and the vmid ratio as 1/2 (vmid_ctrl = 1). this gives vmid = 1.2v. vmid cannot be used as the ldo reference voltage so use the bandgap voltage as the ldo reference voltage (ldo_ref_sel = 1, bg_ena = 1). the default bandgap voltage is 1.467v. for ldovout of 2.4v ldovsel should be set to 2.4v / 1.467v = 1.636. referring to table 38 ldo_vsel = 03h will give ldovout = 1.467 * 1.66 = 2.435v. note that the bnadgap voltage is not trimmed so if required the bandgap voltage can be changed (bg_vsel C see table 39 ) to get closer to the required voltage. by default, the ldo output is actively discharged to gnd through internal resistors when the ldo is disabled. this is desirable in shut-down to prevent any external connections being affected by the internal circuits. the ldo output can be set to float when the ldo is disabled; this is selected by setting the ldo_op_flt bit. this option should be selected if the ldo is bypassed and an external voltage is applied to ldovou t. the ldo output is monitored for voltage accuracy. the ldo undervoltage status can be read at any time from the ldo_uv_sts bit, as described in table 37 . this bit can be polled at any time, or may output directly on a gpio pin, or may be used to generate interrupt events.
WM8944B rev 4. 3 61 register address bit label default description r7 (07h) additional control 7 bias_src 0 bias source select 0 = master bias 1 = start - up bias r17 (11h) status flags 0 ldo_uv_sts 0 ldo undervoltage status (read only) 0 = normal 1 = undervoltage r53 (35h) ldo 15 ldo_ena 0 ldo enable 0 = disabled 1 = enabled 14 ldo_ref_sel_f ast 0 ldo voltage reference select 0 = vmid (normal) 1 = vmid (fast start) this field is only effective when ldo_ref_sel = 0 13 ldo_ref_s el 0 ldo voltage reference select 0 = vmid 1 = bandgap 12 ldo_opflt 0 ldo output float 0 = disabled (output discharged when disabled) 1 = enabled (output floats when disabled) 4:0 ldo_vsel [4:0] 00111 ldo voltage select (sets the ldo output as a ratio of the selected voltage reference. the voltage reference is set by ldo_ref_sel.) 00111 = vref x 1.97 (default) (see table 38 for range) r54 (36h) bandgap 15 bg_ena 0 bandgap reference control 0 = disabled 1 = enab led 4:0 bg_vsel [4:0] 01010 bandgap voltage select (sets the bnadgap voltage) 00000 = 1.200v 26.7mv steps table 37 ldo regulator control
WM8944B 62 rev 4. 3 ldo_vsel [4:0] ldo output ldo_vsel [4:0] ldo output 00h v r ef x 1.42 10h v r ef x 2.85 01h v r ef x 1.50 11h v r ef x 3.00 02h v r ef x 1.58 12h v r ef x 3.16 03h v r ef x 1.66 13h v r ef x 3.32 04h v r ef x 1.74 14h v r ef x 3.49 05h v r ef x 1.82 15h v r ef x 3.63 06h v r ef x 1.90 16h v r ef x 3.79 07h v r ef x 1.97 17h v r ef x 3.95 08h v r ef x 2.06 18h v r ef x 4.12 09h v r ef x 2.13 19h v r ef x 4.28 0ah v r ef x 2.21 1ah v r ef x 4.42 0bh v r ef x 2.29 1bh v r ef x 4.58 0ch v r ef x 2.37 1ch v r ef x 4.7 5 0dh v r ef x 2.45 1dh v r ef x 4.90 0eh v r ef x 2.53 1eh v r ef x 5.06 0fh v r ef x 2.69 1fh v r ef x 5.23 note C v r ef is the applicable voltage reference, selected by ldo_ref_sel. table 38 ldo output voltage control bg_vsel [4:0] bg voltage (v) bg_vsel [4:0] bg voltage (v) 00h 1.200 08h 1. 414 01h 1. 227 09h 1.4 4 0 02h 1. 253 0ah 1. 467 03h 1. 280 0bh 1. 494 04h 1. 307 0ch 1. 520 05h 1. 334 0dh 1. 547 06h 1. 360 0eh 1. 574 07h 1. 387 0fh 1.600 table 39 bandgap voltage control reference voltages and master bias this section describes the analogue reference voltage and bias current controls. it also describes the vmid soft-start circuit for pop suppressed start- up and shut -down. the analogue circuits in the WM8944B require a mid-rail analogue reference voltage, vmid. this reference is generated via a programmable resistor chain. together with the external decoupling capacitor (connected to the vmidc pin), the programmable resistor chain results in a slow, normal or fa st charging characteristic on the vmid reference . this is enabled using vmid_ena and vmid_sel. the different resistor options controlled by vmid_sel can be used to optimize the reference for normal operation, low power standby or for fast start-up as described in table 40. the vmid resistor chain can be powered from the ldo output (ldovout) or from the ldo supply (ldovdd). this is selected using vmid_ref_sel. note that when vmid is selected as the ldo reference voltage, vmid cannot be generated from the ldovout supply voltage (vmid_ref_sel = 1) and must be generated from the ldovdd supply voltage (vmid_ref_sel = 0). the vmid ratio can be selected using vmid_ctrl. this selects the ratio of vmid to the supply voltage that has been selected by vmid_ref_sel. vmid should be half of the ldovout supply voltage for maximum voltage swing. in the case where vmid_ref_sel has selected the ldovout supply voltage , then vmid_ctrl should select the ratio 1/2. in the case where vmid_ref_sel
WM8944B rev 4. 3 63 has selected the ldovdd supply voltage , then the alternate ratio 5/11 may be preferred , as described below. note that the 5/11 ratio is designed for the case where ldovdd = 3.3v and ldovout = 3.0v. this results in a vmid = 3.3v x (5/11) = 1.5v which is half of the ldovout voltage. if these conditions are not being used or the ldo has been bypassed then vmid_ref should be set to select ldovout as the vmid source and vmid_ctrl should be set to select the ratio 1/2. the speaker output drivers require a mid-rail reference voltage. the default operating conditions assume spkvdd >= 3.0v, and use vmid as the reference. the reference can also be adjusted for spkvdd = 1.8v. if spkvdd = 1.8v, then the spk_lowvmid_ena register should be set to 1. this selects a 0.9v mi d-rail reference, enabling optimal power and thd performance at the lower spkvdd voltage. note that the speaker output reference is fixed with respect to ldovout or ldovdd; it does not scale with spkvdd. therefore, the speaker reference cannot be otimised for all spkvdd conditions. if spkvdd > 1.8v and < 3.0v, then spk_lowvmid_ena should be set to 1, but the thd performance may be degraded. the analogue circuits in the WM8944B require a bias current. the normal (master) bias current is enabled by setting bias_ena. note that the master bias current source requires vmid to be enabled also. the master reference and bias control bits are defined in table 40. register address bit label default description r7 (07h) additional control 10 vmid_ref_sel 0 vmid source select 0 = ldo supply ( ldovdd ) 1 = ldo output ( ldovout ) 9 vmid_ctrl 0 vmid ratio control sets the ratio of vmid to the source selected by vmid_ref_sel 0 = 5/11 1 = 1/2 4 vmid_ena 0 vmid enable 0 = disabled 1 = enabled r2 (02 h) power management 1 5 spk_lowvmid_ ena 0 selects 0.9v midrail voltage for speaker output drivers 0 = disabled 1 = enabled this bit should be enabled if spkvdd = 1.8v 3 bias_ena 0 master bias enable 0 = disabled 1 = enabled 1:0 vmid_sel [1:0] 00 vmid d ivider enable and select 00 = vmid disabled (for off mode) 01 = 2 x 50k ? ? ? table 40 reference voltages and master bias enable a pop-suppressed start-up requires vmid to be enabled smoothly, without the step change normally associated with the initial stage of the vmid capacitor charging. a pop-suppressed start-up also
WM8944B 64 rev 4. 3 requires the analogue bias current to be enabled throughout the signal path prior to the vmid reference voltage being applied. the WM8944B incorporates pop-suppression circuits which address these requirements. an alternate bias current source (start-up bias) is provided for pop-free start-up; this is enabled by the startup_bias_ena register bit. the start-up bias is selected (in place of the master bias) using the bias_src bit. it is recommended that the start-up bias is used during start-up, before switching back to the higher quality, normal bias. a s oft -start circuit is provided in order to control the switch-on of the vmid reference. the soft-start control circuit offers two slew rates for enabling the vmid reference; these are selected and enabled by vmid_ramp. when the soft-start circuit is enabled prior to enabling vmid_sel, the reference voltage rises smoothly, without the step change that would otherwise occur. it is recommended that the soft-start circuit and the output signal path be enabled before vmid is enabled by vmid_sel. a soft shut-down is provided, using the soft-start control circuit and the start-up bias current generator. the soft shut-down of vmid is achieved by setting vmid_ramp, startup_bias_ena and bias_src to select the start-up bias current and soft-start circuit prior to setting vmid_sel=00. the internal ldo (described in the previous section) requires a voltage reference. under normal operating conditions, this is provided from vmid, via the register controls described in table 40. note, however, that vmid is normally generated from the ldo output. therefore, an alternative voltage reference is required for start-up, which is not dependent on the ldo output. the vmid_fast_start bit enables a fast - start reference powered from ldovdd. this alternate vmi d can be selected as the ldo reference using the ldo_ref_sel_fast bit as described in table 37. the vmid soft - start and fast start register controls are defined in table 41. register address bit label def ault description r7 (07h) additional control 11 vmid_fast_sta rt 0 vmid (fast - start) enable 0 = disabled 1 = enabled 8 startup_bias_ ena 0 start - up bias enable 0 = disabled 1 = enabled 7 bias_src 0 bias source select 0 = master bias 1 = start - up bias 6:5 vmid_ramp [1:0] 00 vmid soft start enable / slew rate control 00 = disabled 01 = fast soft start 10 = normal soft start 11 = slow soft start table 41 soft start control
WM8944B rev 4. 3 65 pop suppression control the WM8944B incorporates a number of features which are designed to suppress pops normally associated with start-up, sh ut -down or signal path control. these include the option to maintain an analogue output to vmid even when the output driver is disabled. in addition, there is the ability to actively discharge an output to gnd. note that, to achieve maximum benefit from these features, careful attention may be required to the sequence and timing of these controls. disabled output control the line outputs and speaker outputs are biased to vmid in normal operation. in order to avoid audible pops caused by a disabled signal path dropping to gnd, the WM8944B can maintain these connections at vmid when the relevant output stage is disabled. this is achieved by connecting a buffered vmid reference to the output. the buffered vmid reference is enabled by setting vmid_buf_ena. this is applied to any disabled outputs, provided that the respective _vmid_op_ena bit is also set. the output resistance can be either 1k ? or 20k ? , depending on the respective _vroi register bit. the disabled output control bits are described in table 42 . see output signal path for details of how to disable any of the audio outputs. register address bit label default description r2 (02h) power man agement 1 2 vmid_buf_ena 0 vmid buffer enable. (the buffered vmid may be applied to disabled input and output pins. ) 0 = d isabled 1 = e nabled r42 (2ah) output ctrl 13 spkn _vmid_op _ena 0 buffered vmid to spkoutn enable 0 = d isabled 1 = e nabled 12 spkp _vm id_op _ena 0 buffered vmid to spkoutp enable 0 = disabled 1 = enabled 10 line_vmid_op_ ena 0 buffered vmid to lineout enable 0 = disabled 1 = enabled 1 spk _vroi 0 buffered vref to spkoutp / spkoutn resistance (disabled outputs) 0 = approx 20k ohms 1 = ap prox 1k4 ohms 0 line_vroi 0 buffered vref to lineout resistance (disabled output) 0 = approx 20k ohms 1 = approx 1k1 ohms table 42 disabled output control output discharge control the line outputs and speaker output s can be actively discharged to gnd through internal resistors if desired. this is desirable at start-up in order to achieve a known output stage condition prior to enabling the soft-start vmid reference voltage. this is also desirable in shut-down to prevent the external connections from being affected by the internal circuits. the individual control bits for discharging each audio output are described in table 43.
WM8944B 66 rev 4. 3 register address bit label default description r42 (2ah) output ctrl 7 spkn _d isch 0 discharges spkoutn output via approx 550 ohm resistor 0 = not active 1 = a ctively discharging spkoutn 6 spkp _disch 0 discharges spkoutp output via approx 550 ohm resistor 0 = not active 1 = actively discharging spkoutp 4 line_disch 0 discharges lineout output via approx 550 ohm resistor 0 = not active 1 = actively discharging lineout table 43 output discharge control digital audio interf ace the digital audio interface is used for inputting dac data into the WM8944B and outputting adc data from it. it uses four pins: ? adcdat - adc / digital microphone data output ? dacdat - dac data input ? lrclk - dac and adc data alignment clock ? bclk - bit clock, for synchronisation master and slave mode operation the digital audio interface can be configured as a master or a slave interface, using the mstr register bit. the two modes are illustrated in figure 19 and figure 20. figure 19 master mode figure 20 slave mode in master mode, lrclk and bclk are configured as outputs, and the WM8944B controls the timing of the data transfer on the adc dat and dacdat pins. in master mode, the lrclk frequency is determined automatically according to the sample rate (see clocking and sample rates). the bclk frequency is set by the bclk_div register. bclk_div must be set to an appropriate value to ensure that there are sufficient bclk cycles to transfer the complete data words from the adcs and to the dacs. in slave mode, lrclk and bclk are configured as inputs, and the data timing is controlled by an external master. WM8944B adcdat lrclk dacdat bclk processor WM8944B processor adcdat lrclk dacdat bclk
WM8944B rev 4. 3 67 register address bit label default des cription r6 (06h) clock gen control 3:1 bclk_div [2:0] 011 bclk frequency (master mode) 000 = sysclk 001 = sysclk / 2 010 = sysclk / 4 011 = sysclk / 8 100 = sysclk / 16 101 = sysclk / 32 110 = reserved 111 = reserved 0 mstr 0 digital audio interface mo de select 0 = s lave mode 1 = m aster mode table 44 digital audio interface control audio data formats three basic audio data formats are supported: ? left justified ? i 2 s ? dsp mode all of these modes are msb first. they are described in audio data formats, below. refer to the electrical characteristic section for timing information. pcm operation is supported using the dsp mode. the WM8944B is largely a mono device. in the default configuration, the WM8944B transmits adc data on the left channel only of the digital audio interface, and receives dac data on the left channel. the WM8944B also supports a stereo digital microphone interface, enabling stereo output on the digital audio interface (adcdat pin). the digital audio interface transmit configuration can be set using the adcr_src and adcl_src bits; the dac receive channel can be selected using the dac_src bit. digital inversion of the adc and dac data is also possible. the register bits controlling audio data format and channel configuration are described in table 45. register address bit label default description r4 (04h) audio interface 9 adcr_src 1 right digital audio interface source 0 = adc / left dmic data is output on right channel 1 = right dmic data is output on right channel 8 adcl_src 0 left digital audio interface source 0 = adc / left dmic data is output on left channel 1 = right dmic data is output on left channel 6 dac_src 0 dac data source select 0 = dac outputs left interface data 1 = da c outputs right interface data 5 bclk_inv 0 bclk invert 0 = bclk not inverted 1 = bclk inverted
WM8944B 68 rev 4. 3 register address bit label default description 4 lrclk_inv 0 lrclk polarity / dsp mode a - b select. left justified and i 2 s modes C lrclk polarity 0 = not inverted 1 = inverted dsp mode C mode a - b select 0 = msb is available on 2 nd bclk rising edge after lrclk rising edge (mode a) 1 = msb is available on 1 st bclk rising edge after lrclk rising edge (mode b) 3:2 wl [1:0] 10 digital audio interface word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 3 2 bits note C see companding for the selection of 8 - bit mode. 1:0 fmt [1:0] 10 digital audio interface format 00 = reserved 01 = left justified 10 = i2s format 11 = dsp/pcm mode r21 (15h) dac control 1 0 dac_datinv 0 dac data invert 0 = dac output not inverted 1 = dac output inverted r25 (19h) adc control 1 1 adcr_datinv 0 right dmic data invert 0 = right dmic output not inverted 1 = right dmic output inverted 0 adcl_datinv 0 adc / left dmic data invert 0 = adc / left dmic output not inverted 1 = ad c / left dmic inverted table 45 audio data format control in left justified mode, the msb is available on the first rising edge of bclk following a lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles before each lrclk transition. figure 21 left justified audio interface (assuming n-bit word length) n n-1 n-2 3 2 1 n n-1 n-2 3 2 1 left channel right channel msb lsb input word length (wl) 1/fs lrclk bclk dacdat/ adcdat
WM8944B rev 4. 3 69 in i 2 s mode, the msb is available on the second rising edge of bclk following a lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of one sample and the msb of the next. figure 22 i 2 s justified audio interface (assuming n-bit word length) in dsp/pcm mode, the left channel msb is available on either the 1 st (mode b) or 2 nd (mode a) rising edge of bclk (selected by lrclk_inv) following a rising edge of lrclk . right channel data immediately follows left channel data. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of the right channel data and the next sample. in device master mode, the lrclk output resembles the frame pulse shown in figur e 23 and figure 24 . in device slave mode, figure 25 and figure 26 , it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one bclk period before the rising edge of the next frame pulse. figur e 23 dsp/pcm mode audio interface (mode a, lrclk_inv=0, master) figure 24 dsp/pcm mode audio interface (mode b, lrclk_inv=1, master) n n-1 n-2 3 2 1 n n-1 n-2 3 2 1 left channel right channel msb lsb input word length (wl) 1/fs lrclk bclk dacdat/ adcdat 1 bclk 1 bclk n n-1 n-2 3 2 1 n n-1 n-2 3 2 1 left channel right channel msb lsb input word length (wl) 1/fs lrclk bclk dacdat/ adcdat 1 bclk 1/2fs n n-1 n-2 3 2 1 n n-1 n-2 3 2 1 left channel right channel msb lsb input word length (wl) 1/fs lrclk bclk dacdat/ adcdat 1/2fs
WM8944B 70 rev 4. 3 figure 25 dsp/pcm mode audio interface (mode a, lrclk_inv=1, slave) figure 26 dsp/pcm mode audio interface (mode b, lrclk_inv=1, slave) companding the WM8944B supports a-law and ? -law companding on both transmit (adc) and receive (dac) sides as shown in table 46 . companding converts 13 bits ( ? -law) or 12 bits (a-law) to 8 bits using non -linear quantization. this provides greater precision for low-amplitude signals than for high-amplitude signals, resulting in a greater usable dynamic range than 8 bit linear quantization. register address bit label default description r5 (05h) companding control 3 dac_comp 0 dac companding enable 0 = disabled 1 = enabled 2 dac_ compmo de 0 dac c ompanding m ode 0 = - law 1 = a - law 1 adc_comp 0 adc companding enable 0 = disabled 1 = enabled 0 adc_compmo de 0 adc c ompanding m ode 0 = - law 1 = a - law table 46 companding control n n-1 n-2 3 2 1 n n-1 n-2 3 2 1 left channel right channel msb lsb input word length (wl) 1/fs lrclk bclk dacdat/ adcdat 1 bclk falling edge can occur anywhere in this area 1 bclk n n-1 n-2 3 2 1 n n-1 n-2 3 2 1 left channel right channel msb lsb input word length (wl) 1/fs lrclk bclk dacdat/ adcdat 1 bclk 1 bclk falling edge can occur anywhere in this area
WM8944B rev 4. 3 71 companding uses a piecewise linear approximation of the following equations (as set out by itu- t g.711 standard) for data compression: ? -law (where ? =255 for the u.s. and japan): f(x) = ln( 1 + ? |x|) / ln( 1 + ? ) } for - 1 x 1 a-law (where a=87.6 for europe): f(x) = a|x| / ( 1 + lna) ? for x 1/a f(x) = ( 1 + lna|x|) / (1 + lna) ? for 1/a x 1 figure 27 -law companding figure 28 a-law companding u-law companding 0 20 40 60 80 100 120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output a-law companding 0 20 40 60 80 100 120 0 0.2 0.4 0.6 0.8 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output
WM8944B 72 rev 4. 3 the companded data is also inverted as recommended by the g.711 standard (all 8 bits are inverted for ? -law, all even data bits are inverted for a-law). companded data is transmitted in the first 8 msbs of its respective data word, and consists of sign (1 bit), exponent (3 bits) and mantissa (4 bits), as shown in table 47. bit7 bit[6:4] bit[3:0] sign exponent mantissa table 47 8-bit companded word composition 8-bit mode is selected whenever dac_comp=1 or adc_comp=1. the use of 8-bit data allows samples to be passed using as few as 8 bclk cycles per left/right clock frame. when using dsp mode b, 8-bit data words may be transferred consecutively every 8 bclk cycles. 8-bit mode (without companding) may be enabled by setting dac_compmode=1 or adc_compmode=1, when dac_comp=0 and adc_comp=0. audio interface loopback a loopback function is provided for test and evaluation purposes. when the loopback register bit is set, the dac input data is fed through the dsp core to the left adc output, as illustrated in figure 29. note that this is only possible when adcl_ena = 1 and adcr_ena = 0. there is no output on the right adc channel when the audio interface loopback is enabled. figure 29 audio interface loopback digital audio interface dacdat adcdat lrclk bclk adc dac audio interface loopback mode se1 (lpf/hpf, 3d surround, 5-notch, df1) se2 (hpf, re-tune, 5-band eq) se3 (dynamic range control)
WM8944B rev 4. 3 73 register address bit label default description r5 (05h) companding control 5 loopback 0 audio interface loopback function 0 = no loopback 1 = audio interface loopback enabled (dacdat input is fed through the dsp core to the adcdat output). table 48 audio interface loopback control adc to da c loopback a loopback function is also provided to allow the adc digital data output to be fed internally to the dac data input. this function is enabled by adc_dac_loopback and is illustrated in figure 30. figure 30 adc to dac loopback register address bit label default description r5 (05h) companding control 15 adc_dac_loo pback adc to dac loopb ack function 0 = no loopback 1 = adc to dac loopback enabled (adc data is fed directly into dac data input). table 49 adc to dac loopback control dacdat adcdat lrclk bclk dac adc to dac loopback mode se1 (lpf/hpf, 5-notch, df1) se2 (hpf, re-tune, 5-band eq) se3 (dynamic range control) adc digital audio interface
WM8944B 74 rev 4. 3 digital pull-up and pull-down the WM8944B provides integrated pull-up and pull-down resistors on each of the dacdat, lrclk and bclk pins. this provides a flexible capability for interfacing with other devices. each of the pull- up and pull-down resistors can be configured independently using the register bits described in table 50. register address bit label default description r4 (04h) audio interface 15:14 dacdata_pul l [1:0] 00 dacdat pull - up / pull - down enable 00 = no pull - up or pull - down 01 = pull - down 10 = pull - up 11 = reserved 13:12 frame_pull [1:0] 00 lr clk pull - up / pull - down enable 00 = no pull - up or pull - down 01 = pull - down 10 = pull - up 11 = reserved 11:10 bclk_pull [1:0] 00 bclk pull - up / pull - down enable 00 = no pull - up or pull - down 01 = pull - down 10 = pull - up 11 = reserved table 50 pull-up and pull-down control clocking and sample rates the internal clocks for the codec and digital audio interface are derived from a common internal clock source, sysclk. this clock can either be derived directly from mclk, or may be genera ted using the frequency locked loop (fll) using mclk as a reference. all commonly-used audio sample rates can be derived directly from typical mclk frequencies; the fll provides additional flexibility for a wider range of mclk frequencies. the WM8944B supports a wide range of standard audio sample rates from 8khz to 48khz. when the adc and dac are both enabled, they operate at the same sample rate, fs. other functions such as the interrupts and gpio input de-bounce are clocked using a free-running oscillato r. the control registers associated with clocking and sample rates are described in table 51. the overall clocking scheme for the WM8944B is illustrated in figure 31.
WM8944B rev 4. 3 75 figure 31 WM8944B clocking overview sysclk may be derived either from mclk or from the fll; this is selected using the sysclk_src register bit. sysclk is enabled using the sysclk_ena and may be modified using a programmable divider configured by sysclk_div. the sysclk_rate register must be set according to the ratio of sysclk to the audio sample rate. it is required that sysclk_div is correctly set in order to produce either 512 x fs or 256 x fs at its output, where fs is the audio sampl ing rate. the sampling rate for the codec and digital audio interface is configured using the sr register field. in master mode, the frequency of the left/right clock output on the lrclk pin is the bclk frequency divided by 64 producing 32 bclk cycles per channel. in master mode, the bclk_div register configures the bit clock frequency output on bclk. the WM8944B can output a configurable clock on the gpio pins; this is enabled automatically whenever a gpio pin is configured for clkout output. the source can either be before or after the sysclk divider, as shown in figure 31 . the source is selected using clkout_sel, and may be modified using a programmable divider configured by clkout_div. the WM8944B free-running oscillator required for gpio input de-bounce and interrupt functions must be enabled using osc_clk_ena whenever any of these functions is required. register address bit label default description r6 (06h) clock gen control 15 osc_clk_ena 0 oscillator enable 0 = d isabled 1 = e nabled this needs to be set when a timeout clock is required for gpio input detection 14:13 mclk_pull [1:0] 00 mclk pull - up / pull - down enable 00 = no pull - up or pull - down 01 = pull - down 10 = pull - up 11 = reserved mclk f out sysclk_src sysclk_ena sysclk_div [2:0] codec dsp f/n lrclk bclk mstr fll f ref sr [3:0] sysclk_rate clkout_sel clkout_div [1:0] f/n clkout clkout may be output on a gpio pin f/n bclk_div [2:0] master mode clock outputs oscillator osc_clk_ena toclk_ena clocking for gpio de-bounce and interrupt functions clocking for pga zero-cross timeouts f/64 fll_ena fll_clk_ref_div fll_n fll_k fll_fratio fll_frac fll_outdiv sysclk (512 x fs) or (256 x fs)
WM8944B 76 rev 4. 3 register address bit label default description 12 clkout_sel 0 clkout source select 0 = sysclk 1 = f ll or mclk (set by sysclk_src register) 11:10 clkout_div [1:0] 00 clkout clock divider 00 = divide by 1 01 = divide by 2 10 = divide by 4 11 = divide by 8 9 sysclk_ena 0 sysclk enable 0 = d isabled 1 = e nabled 8 sysclk_src 0 sysclk so urce select 0 = mclk 1 = fll out put 7:5 sysclk_div [2:0] 000 sysclk clock divider ( sets the scaling for either the mclk or fll clock output , depending on sysclk_src) 000 = divide by 1 001 = divide by 1.5 010 = divide by 2 011 = divide by 3 100 = divide b y 4 101 = divide by 6 110 = divide by 8 111 = divide by 12 4 toclk_ena 0 toclk enabled ( enable s timeout clock for gpio level detection ) 0 = disabled 1 = enabled r7 (07h) additional control 15 sysclk_rate 1 selects the sysclk / fs ratio 0 = sysclk = 256 x fs 1 = sysclk = 512 x fs 3:0 sr [3:0] 1101 audio sample rate select 0011 = 8khz 0100 = 11.025khz 0101 = 12khz 0111 = 16khz 1000 = 22.05khz 1001 = 24khz 1011 = 32khz 1100 = 44.1khz 1101 = 48khz table 51 clocking and sample rate control
WM8944B rev 4. 3 77 digital mic clocking when any gpio is configured as dmic clk output, the WM8944B outputs a clock which supports digital mic operation at the adc sampling rate. although the adc is not used, the sysclk and sample rate control fields must still be set as they would for adc operation. the clock frequencies for each of the sample rates is shown in table 52. pcm sample rate dmicclk fs rate 8khz 1.024mhz 128fs 11.025khz 1.411mhz 128fs 12khz 1.536mhz 128fs 16khz 2.048mhz 128 fs 22.05khz 2.8224mhz 128fs 24khz 3.072mhz 128fs 32khz 2.048mhz 64fs 44.1khz 2.8224mhz 64fs 48khz 3.072mhz 64fs table 52 digital microphone clock frequencies frequency locked loop (fll) the integrated fll can be used to generate sysclk from a wide variety of different reference sources and frequencies. the fll uses mclk as its reference, which may be a high frequency (eg. 12.288mhz) or low frequency (eg. 32,768khz) reference. the fll is tolerant of jitter and may be used to generate a stable sysclk from a less stable input signal. the fll characteristics are summarised in electrical characteristics. the fll control registers are described in figure 32. figure 32 fll configuration the fll is enabled using the fll_ena register bit. note that, when changing fll settings, it is recommended that the digital circuit be disabled via fll_ena and then re-enabled after the other register settings have been updated. when changing the input reference frequency f ref , it is recommended that the fll be reset by setting fll_ena to 0. the field fll_clk_ref_div provides the option to divide the input reference (mclk) by 1, 2, 4 or 8. this field should be set to bring the reference down to 13.5mhz or below. for best performance, it is recommended that the highest possible frequency C within the 13.5mhz limit C should be selected. the field fll_ctrl_rate controls internal functions within the fll; it is recommended that only the default setting be used for this parameter. fll_gain controls the internal loop gain and should be set to the recommended value. the fll output frequency is directly determined from fll_fratio, fll_outdiv and the real number represented by fll_n and fll_k. the field fll_n is an integer (lsb = 1); fll_k is the fractional portion of the number (msb = 0.5). the fractional portion is only valid when enabled by the field fll_frac. power consumption in the fll is reduced in integer mode; however, the performance may also be reduced, with increased noise or jitter on the output. if low power consumption is required, then fll settings must be chosen where n.k is an integer (ie. fll_k = 0). in this case, the fractional mode can be disabled by setting fll_frac = 0. f vco f out 90mhz < fvco < 100mhz fll_outdiv = 4, 8, 16, 32 fll_fratio = 1, 2, 4, 8, 16 multiply by n.k n.k = real number divide by fll_clk_ref_div f ref fll_clk_ref_div = 1, 2, 4, 8 f ref <13.5mhz divide by fll_outdiv multiply by fll_fratio mclk
WM8944B 78 rev 4. 3 for best fll performance, a non-integer value of n.k is required. in this case, the fractional mode must be enabled by setting fll_frac = 1. the fll settings must be adjusted, if necessary, to produce a non-integer value of n.k. the fll output frequency is generated according to the following equation: f out = (f vco / fll_outdiv) the fll operating frequency, f vco is set according to the following equation: f vco = (f ref x n.k x fll_fratio) f ref is the input frequency, as determined by fll_clk_ref_div. f vco must be in the range 90-100 mhz. frequencies outside this range cannot be supported. note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed across the full range of device operating temperatures. in order to follow the above requirements for f vco , the value of fll_outdiv should be selected according to the desired output f out , as described in table 53. output frequency f out fll_outdiv 2.8125 mhz C C C C C table 53 selection of fll_outdiv the value of fll_fratio should be selected as described in table 54. reference frequency f ref fll_fratio 1mhz - 13.5mhz 0h (divide by 1) 256khz - 1mhz 1h (divide by 2) 128khz - 256khz 2h (divide by 4) 1 6khz - 128khz 3h (divide by 8) less than 1 6khz 4h (divide by 16) table 54 selection of fll_fratio in order to determine the remaining fll parameters, the fll operating frequency, f vco , must be calculated, as given by the following equation: f vco = (f out x fll_outdiv) the value of fll_n and fll_k can then be determined as follows: n.k = f vco / (fll_fratio x f ref ) note that f ref is the input frequency, after division by fll_clk_ref_div, where applicable.
WM8944B rev 4. 3 79 in fll fractional mode, the fractional portion of the n.k multiplier is held in the fll_k register field. this field is coded as a fixed point quantity, where the msb has a weighting of 0.5. note that, if desired, the value of this field may be calculated by multiplying k by 2^16 and treating fll_k as an integer value, as illustrated in the following example: if n.k = 8.192, then k = 0.192. multiplying k by 2^16 gives 0.192 x 65536 = 12582.912 (decimal) apply rounding to the nearest integer = 12583 (decimal) = 3127 (hex) for best fll performance, the fll fractional m ode is recommended. therefore, if the calculations yield an integer value of n.k, then it is recommended to adjust fll_fratio in order to obtain a non- integer value of n.k. care must always be taken to ensure that the fll operating frequency, f vco , is within its recommended limits of 90-100 mhz. the register fields that control the fll are described in table 55 . example settings for a variety of reference frequencies and output frequencies are shown in table 56. register address bit label default description r8 (08h) fll control 1 12:11 fll_clk_re f_div [1:0] 00 fll clock reference divider 00 = mclk / 1 01 = mclk / 2 10 = mclk / 4 11 = mclk / 8 mclk must be div ided down to <=13.5mhz. for lower power operation, the reference clock can be divided down further if desired. 10:8 fll_outdiv [2:0] 001 f out clock divider 000 = 2 001 = 4 010 = 8 011 = 16 100 = 32 101 = 64 110 = 6 111 = 12 (f out = f vco / fll_outdiv) 7:5 fll_ctrl_r ate [2:0] 000 frequency of the fll control block 000 = f vco / 1 (recommended value) 001 = f vco / 2 010 = f vco / 3 011 = f vco / 4 100 = f vco / 5 101 = f vco / 6 110 = f vco / 7 111 = f vco / 8 recommended that this register is not change d from default.
WM8944B 80 rev 4. 3 register address bit label default description 4:2 fll_fratio [2:0] 000 f vco clock divider 000 = 1 001 = 2 010 = 4 011 = 8 1xx = 16 000 recommended for f ref > 1m hz 100 recommended for f ref < 16khz 011 recommended for all other cases 1 fll_frac 1 fractional enable 0 = integer mode 1 = fractional mode integer mode offers reduced power consumption. fractional mode offers best fll performance, provided also that n.k is a non - integer value. 0 fll_ena 0 fll enable 0 = disabled 1 = enabled r9 (09h) fll control 2 15:0 fll_k [15:0] 3127h fractional multiply for f ref (msb = 0.5) r10 (0ah) fll control 3 14:5 fll_n [9:0] 008h integer multiply for f ref (lsb = 1) 3:0 fll_gain [3:0] 0000 gain applied to error 0000 = x 1 (recommended value) 0001 = x 2 0010 = x 4 0011 = x 8 0100 = x 16 0101 = x 32 0110 = x 64 0111 = x 128 1000 = x 256 recommended that this register is not changed from default. table 55 frequency locked loop control
WM8944B rev 4. 3 81 example fll calculat ion to generate 24.576 mhz output (f out ) from a 12.000mhz reference clock (f ref ): ? set fll_clk_ref_div in order to generate f ref <=13.5mhz: fll_clk_ref_div = 00 (divide by 1) ? set fll_ctrl_rate to the recommended setting: fll_ctrl_rate = 000 (divide by 1) ? sett fll_gain to the recommended setting: fll_gain = 0000 (multiply by 1) ? set fll_outdiv for the required output frequency as shown in table 53 :- f out = 24.576mhz, therefore fll_outdiv = 1 h (divide by 4) ? set fll_fratio for the given reference frequency as shown in table 54: f ref = 12mhz, therefore fll_fratio = 0h (divide by 1) ? calculate f vco as given by f vco = f out x fll_outdiv:- f vco = 24.576 x 4 = 98.304mhz ? calculate n.k as given by n.k = f vco / (fll_fratio x f ref ): n.k = 98.304 / (1 x 12) = 8.192 ? determine fll_n and fll_k from the integer and fractional portions of n.k:- fll_n is 8(dec) = 008(hex). fll_k is 0.192 (dec) = 3127 (hex). ? confirm that n.k is a fractional quantity and set fll_frac: n.k is fractional. set fll_frac = 1. note that, if n.k is an inte ger, then an alternative value of fll_fratio may be selected in order to produce a fractional value of n.k.
WM8944B 82 rev 4. 3 example fll settings table 56 provides example fll settings for generating common sysclk frequencies from a variety of low and high frequency reference inputs. f ref f out fll_clk_ ref_div f vco fll_n fll_k fll_ fratio fll_ outdiv fll_ frac 8.000 khz 22.5792 mhz divide by 1 (0h) 90.3168 mhz 705 ( 2c1 h ) 0 .6 ( 9999 h) 16 (4 h) 4 ( 1 h) 1 8.000 khz 24.576 mhz divide by 1 (0h) 98.30 4 mhz 768 ( 3 00h ) 0.0 (0000h) 16 (4 h) 4 (1h) 0 32.768 khz 22.5792 mhz divide by 1 (0h) 90.3168 mhz 344 ( 158h ) 0.5 3125 ( 8800h ) 8 (3h) 4 (1h) 1 32.768 khz 24.576 mhz divide by 1 (0h) 98.304 mhz 375 ( 177h ) 0.0 (0000h) 8 (3h) 4 (1h) 0 768.000 khz 22.5792 mhz divide by 1 (0h) 90.3168 mhz 14 (00eh) 0.7 (b333h) 8 (3h) 4 (1h) 1 768.000 khz 24.576 mhz divide by 1 (0h) 98.304 mhz 16 (010h) 0.0 (0000h) 8 (3h) 4 (1h) 0 1.024 mhz 22.5792 mhz divide by 1 (0h) 90.3168 mhz 88 (058h) 0.2 (3333h) 1 (0h) 4 (1h) 1 1.024 m hz 24.576 mhz divide by 1 (0h) 98.304 mhz 96 (060h) 0.0 (0000h) 1 (0h) 4 (1h) 0 6.144 mhz 22.5792 mhz divide by 1 (0h) 90.3168 mhz 14 (00eh) 0.7 (b333h) 1 (0h) 4 (1h) 1 6.144 mhz 24.576 mhz divide by 1 (0h) 98.304 mhz 16 (010h) 0.0 (0000h) 1 (0h) 4 (1h) 0 11.2896 mhz 22.5792 mhz divide by 1 (0h) 90.3168 mhz 8 (008h) 0.0 (0000h) 1 (0h) 4 (1h) 0 11.2896 mhz 24.576 mhz divide by 1 (0h) 98.304 mhz 8 (008h) 0.70749 ( b51eh ) 1 (0h) 4 (1h) 1 12.000 mhz 22.5792 mhz divide by 1 (0h) 90.3168 mhz 7 (007h) 0.5264 ( 86c2h) 1 (0h) 4 (1h) 1 12.000 mhz 24.576 mhz divide by 1 (0h) 98.304 mhz 8 (008h) 0.192 ( 3127h ) 1 (0h) 4 (1h) 1 12.288 mhz 22.5792 mhz divide by 1 (0h) 90.3168 mhz 7 (007h) 0.35 ( 599ah ) 1 (0h) 4 (1h) 1 12.288 mhz 24.576 mhz divide by 1 (0h) 98.304 mhz 8 (008h) 0.0 (0000h) 1 (0h) 4 (1h) 0 13.000 mhz 22.5792 mhz divide by 1 (0h) 90.3168 mhz 6 (006h) 0.94745 ( f28ch ) 1 (0h) 4 (1h) 1 13.000 mhz 24.576 mhz divide by 1 (0h) 98.304 mhz 7 (007h) 0.56185 (8fd5h) 1 (0h) 4 (1h) 1 19.200 mhz 22.5792 mhz divide by 2 (1h) 90.3168 mhz 9 (009h) 0.408 ( 6873h ) 1 (0h) 4 (1h) 1 19.200 mhz 24.576 mhz divide by 2 (1h) 98.304 mhz 10 (00ah) 0.24 ( 3d71h ) 1 (0h) 4 (1h) 1 27.000 mhz 22.5792 mhz divide by 2 (1h) 90.3168 mhz 6 (006h) 0.69013 ( b0adh ) 1 (0h) 4 (1h) 1 27.000 mhz 24 .576 mhz divide by 2 (1h) 98.304 mhz 7 (007h) 0.28178 ( 4823h ) 1 (0h) 4 (1h) 1 table 56 example fll settings
WM8944B rev 4. 3 83 video buffer the WM8944B provides a current mode output video buffer with an input 3 rd order butterworth low pass filter (lpf) and clamp. the video buffer is powered from ldovdd - typically 3.3v. the video buffer is compatible with pal and ntsc video formats. the low pass filter (lpf) is intended to remove images in the video dac output waveform at multiples of the dac clock frequency. the input clamp supports ac coupling at the input to the video buffer. the current mode output employed by the WM8944B video buffer allows operation at lower supply voltages than voltage mode video buffers. the current mode output also provides inherent protection against short circuits during jack insertion and removal. a current reference resistor (positioned close to the WM8944B) ensures that the signal swing at the output of the buffer is the same as that at the receiving equipment (e.g. a television set), thus providing excellent signal reproduction. for best performance, the input to the video buffer should be ac coupled and terminated to 75 ? . note that the input clamp and pull-down features described below are only applicable to the ac-coupled input configuration. care should be taken with pcb layout, designing for at least 1ghz frequencies to avoid degrading performance. pcb vias and sharp corners should be avoided and parasitic capacitance minimised on signal paths; these should be kept as short and straight as possible. the ldovdd supply should be decoupled as close to the WM8944B as possible. see the external components section for more information. the video buffer is enabled using the vb_ena register bit. the gain of the video buffer is selected using vb_gain; this can be set to 0db or 6db (corresponding to 6db or 12db unloaded). the lpf response can be adjusted by setting the vb_qboost register; this provides a small amount of additional gain in the region of the cut-off frequency. the input signal clamp is enabled using vb_clamp; this controls the dc component of the video signal for compatibility with the WM8944B. the video buffer pull-down can be enabled using vb_pd; this may be used during power-up of the video buffer in order to align the signal levels between the source and the WM8944B. note that the pull-down should not be enabled during normal operation of the video buffer; it should be enabled when the video buffer is first powered up, and subsequently disabled (eg. after 20ms ) once the circuit has settled. a programmable dc offset can be applied to the output signal using the vb_disoff register field; this can be set to 0mv, 20mv or 40mv offset. note that the vmid reference (see voltage references and master bias) must be ena bled when using the WM8944B video buffer. vmid is enabled by setting vmid_ena, as defined in table 40. the video buffer control registers are described in table 57. register address bit la bel default description r38 (26h) video buffer 7 vb_ena 0 video buffer enable 0 = d isabled 1 = e nabled 6 vb_qboost 0 video buffer filter q - boost control 0 = disabled 1 = enabled 5 vb_gain 0 video buffer gain 0 = 0db (=6db unloaded) 1 = 6db (=12db unlo aded)
WM8944B 84 rev 4. 3 register address bit la bel default description 4:3 vb_disoff [1:0] 111 video buffer dc offset control 000 = reserved 001 = 40mv offset 010 = reserved 011 = 20mv offset 100 = reserved 101 = reserved 110 = reserved 111 = 0mv offset note - the specified offset applies to the 0db gain setting (vb_g ain=0). when 6db gain is selected, the dc offset is doubled. 1 vb_pd 0 video buffer pull - down 0 = pull - down disabled 1 = pull - down enabled 0 vb_clamp 0 enable the clamp between the video input and ground 0 = no clamp 1 = video buffer input is clamped t o ground table 57 video buffer control the video buffer circuit is illustrated in figure 33. figure 33 video buffer block diagram the video buffer requires two external resistor components, as illustrated in figure 33 . for best performance, the resistor r source should be matched (equal) to the load impedance r load . the resistance r ref is a function of the circuit gain and a function of the parallel combination of r source and rl oad . when vb_gain = 0 (0db gain), the current gain of the video buffer is 5, as described by the equation i vbout = 5 x i vbref . the resistor r ref should be set equal to 5 x (r source // r load ), where (r source // r load ) is the effective resistance of the parallel combination of r source and r load . (note that the required resistance r ref is the same for both settings of vb_gain.) in a typical application, r load = 75 ? , r source = 75 ? , r ref = 187 ? . ldovdd vbref video buffer vbin vbout tv in 6db / 12db (unloaded) 0db / 6db (fully loaded) lpf clamp r ref r source r load
WM8944B rev 4. 3 85 recommended video buffer initialisation sequence s recommended power-up sequences for video buffer applications are described in table 58 and table 59. description label register [bits] turn on external supplies and wait for the supply voltages to settle. reset registers to default state (software reset) . sw_reset r0 (00h) [15:0] enable vmid fast start and start up bias . select start - up bias and set vmid soft start for start - up ramp. vmid_fast_start = 1 startup_b ias_ena = 1 bias_src = 1 vmid_ramp[1:0] = 01 r7 (07h) [11] r7 (07h) [8] r7 (07h) [7] r7 (07h) [6:5] if using vmid as the reference voltage for the ldo then select vmid fast start or set to 0 if using the bandgap as the reference voltage for ldo. select ld o start - up bias and enable ldo. delay 300ms for ldo to settle. ldo_ena = 1 ldo_ref_sel_fast = 1 ldo_bias_src = 1 r53 (35h) [15] r53 (35h) [14] r53 (35h) [5] enable vmid buffer and master bias. set vmid_sel[1:0] for fast start - up. bias_ena = 1 vmid_buf_en a = 1 vmid_sel[1:0] = 11 r2 (02h) [3] r2 (02h) [2] r2 (02h) [1:0] enable vmid. delay 50ms to allow vmid to settle. vmid_ena = 1 r7 (07h) [4] set ldo and vmid for normal operation. ldo_ref_sel_fast = 0 ldo_bias_src = 0 vmid_fast_start = 0 startup_bias_en a = 0 vmid_sel = 01 r53 (35h) [14] r53 (35h) [5] r7 (07h) [11] r7 (07h) [8] r2 (02h) [1:0] set video buffer gain as required. vb_gain r38 (26h) [5] set video buffer filter q boost as required. vb_qboost r38 (26h) [6] enable video buffer clamp. vb_clamp = 1 r38 (26h) [0] enable video buffer pulldown. vb_pd = 1 r38 (26h) [1] enable video buffer. delay 20ms for buffer to capture input level. vb_ena = 1 r38 (26h) [7] disable video buffer pulldown. vb_pd = 0 r38 (26h) [1] table 58 power-up sequence (video signal ac-coupled to video buffer input)
WM8944B 86 rev 4. 3 description label register [bits] turn on external supplies and wait for the supply voltages to settle. reset registers to default state (software reset) . sw_reset r0 (00h) [15:0] ena ble vmid fast start and start up bias. select start - up bias and set vmid soft start for start - up ramp. vmid_fast_start = 1 startup_bias_ena = 1 bias_src = 1 vmid_ramp[1:0] = 01 r7 (07h) [11] r7 (07h) [8] r7 (07h) [7] r7 (07h) [6:5] if using vmid as the re ference voltage for the ldo then select vmid fast start or set to 0 if using the bandgap as the reference voltage for ldo. select ldo start - up bias and enable ldo. delay 300ms for ldo to settle. ldo_ena = 1 ldo_ref_sel_fast = 1 ldo_bias_src = 1 r53 (35h) [ 15] r53 (35h) [14] r53 (35h) [5] enable vmid buffer and master bias. set vmid_sel[1:0] for fast start - up. bias_ena = 1 vmid_buf_ena = 1 vmid_sel[1:0] = 11 r2 (02h) [3] r2 (02h) [2] r2 (02h) [1:0] enable vmid delay 50ms to allow vmid to settle vmid_ena = 1 r7 (07h) [4] set ldo and vmid for normal operation. ldo_ref_sel_fast = 0 ldo_bias_src = 0 vmid_fast_start = 0 startup_bias_ena = 0 vmid_sel = 01 r53 (35h) [14] r53 (35h) [5] r7 (07h) [11] r7 (07h) [8] r2 (02h) [1:0] set video buffer gain as required vb _gain r38 (26h) [5] set video buffer filter q boost as required vb_qboost r38 (26h) [6] enable video buffer vb_ena = 1 r38 (26h) [7] table 59 power-up sequence (video signal dc-coupled to video buffer input)
WM8944B rev 4. 3 87 general purpose input/output the WM8944B provides two multi-function pins which can be configured to provide a number of different functions. these are digital input/output pins on the dbvdd power domain. the gpio pins are: ? cs /gpio1 ? cifmode/gpio2 note that the gpio pins are shared with control interface functions. the pins available for gpio function depend on the selected control interface mode, as described in table 60. control interface mo de gpio pin availabilit y 2 - wire (i2c) gpio1 gpio2 3 - wire (spi) gpio2 table 60 gpio pin availability note that cif mode/gpio2 pin selects between i2c and spi control interface modes (see control interface). to enable gpio functions on gpio2, the mode_gpio register bit must be set in order to disconnect this pin from the control interface circuit. setting the mode_gpio register bit causes the control interface mode selection to be latched; it will remain latched until a software reset or power on reset occurs. the register fields that control the gpio pins are described in table 61. for each gpio, the selected function is determined by the gpn_ fn field, where n identifies the gpio pin (1 or 2). the pin direction, set by gpn_dir, must be set according to function selected by gpn_sel. when a pin is configured as a gpio output, its level can be set to logic 0 or logic 1 using the gpn_lvl field. when a pin is configured as a gpio input, the logic level can be read from the respective gpn_lvl bit. the gpio output is inverted with respect to the gpn_lvl register when the polarity bit gpn_pol is set; the equivalent is true of gpio inputs also. internal pull-up and pull-down resistors may be enabled using the gpn_pull fields; this allows greater flexibility to interface with different signals from other devices. each of the gpio pins is an input to the interrupt control circuit and can be used to trigger an interrupt event. this may be configured as level-triggered or edge-triggered using the gpn_fn registers. edge detect raises an interrupt when the gpio status changes; level detect asserts the interrupt for as long as the gpio status is asserted. see interrupts. an edge-triggered gpio can be configured to trigger on a single edge or on both edges of the i nput signal; this is selected using the gpn_int_mode registers. a level-triggered or single- edge -triggered input may be configured using the gpn_pol registers to respond to a high level/edge (when gpn_pol = 0) or a low level/edge (when gpn_pol = 1). the gp io control fields are defined in table 61. register address bit label default description r11 (0bh) gpio config 0 mode _gpio 0 cif mode/ gpio2 pin configuration 0 = p in configured as cifmode 1 = pin configured as gpio2 note - when t his bit is set to 1, it is latched and cannot be reset until power - off or software reset. r13 (0dh) gpio1 control 15 gp1 _dir 1 gpio1 pin direction 0 = output 1 = input
WM8944B 88 rev 4. 3 register address bit label default description 14:13 gp1 _pull [1:0] 00 gpio1 pull - up / pull - down enable 00 = no pull - up or pull - down 01 = pull - down 10 = pull - up 11 = reserved 12 gp1 _int_ mode 0 gpio1 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp1 _pol=0) or falling edge triggered (if gp1 _pol =1) 1 = gpio interrupt is triggered on rising and falling edges 10 gp1 _p ol 0 gpio1 polarity select 0 = non - inverted 1 = inverted 5 gp1 _lvl 0 gpio1 level. write to this bit to set a gpio output. read from this bit to read gpio input level. when gp1 _pol is set, the register contains the opposite logic level to the external pin . 3:0 gp1 _fn [3:0] 0000 gpio1 pin function (see table 62 for details) r14 (0eh) gpio2 control 15 gp2 _dir 1 gpio2 pin direction 0 = output 1 = input 14:13 gp2 _pull [1:0] 10 gpio2 pull - up / pull - down enable 00 = no pull - up or p ull - down 01 = pull - down 10 = pull - up 11 = reserved 12 gp2 _int_ mode 0 gpio2 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp2 _pol=0) or falling edge triggered (if gp2 _pol =1) 1 = gpio interrupt is triggered on rising and falling edges 10 gp2 _pol 0 gpio2 polarity select 0 = non - inverted 1 = inverted 5 gp2 _lvl 0 gpio2 level. write to this bit to set a gpio output. read from this bit to read gpio input level. when gp2 _pol is set, the register contains the opposite logic level to the exte rnal pin. 3:0 gp2 _fn [3:0] 0000 gpio2 pin function (see table 62 for details) table 61 gpio control gpio function select the available gpio functions are described in table 62 . the function of each gpio is set using the gpn_fn register, where n identifies the gpio pin (1 or 2 ). note that the polarity of the gpio inputs and outputs may be selected using the gpn_pol register bits. when gpn_pol = 1, then the polarity is inverted with respect to the descriptions below.
WM8944B rev 4. 3 89 the gpio input functions may be used to detect headphone jack insertion or a button press. these signals may be used as inputs to the interrupt controller, via the integrated de-bounce circuit. gpn_fn description comm ents 0000 logic level input external logic level is read from gpn_lvl . associated interrupt (when enabled) is level - triggered. 0001 edge detection input external logic level is read from gpn_lvl. associated interrupt (when enabled) is edge triggered. not e that toclk_ena must be set . 0010 clk out output output clock frequency is set by clkout_div. 0011 interrupt (irq) output hardware output of all unmasked interrupts. 0100 reserved 0101 reserved 0110 reserved 0111 temperature flag output indicates the temperature sensor output. this is a hardware output of the temp_sts bit (assuming gpn_pol = 0). 0 = normal 1 = overtemperature 1000 reserved 1001 dmicclk output output clock for digital microphone interface 1010 logic level output pin logic level is set by gpn_lvl. 1011 ldo_uv output indicates the ldo undervoltage status. this is a hardware output of the ldo_uv_sts bit (assuming gpn_pol = 0). 0 = normal 1 = ldo undervoltage 1100 reserved 1101 reserved 1110 reserved 1111 reserved table 62 gpio function select interrupts the interrupt controller has multiple inputs. these include the gpio input pins, temperature sensor and the ldo regulator. any combination of these inputs can be used to trigger an interrupt (irq) event. there is an interrupt status field associated with each of the irq inputs. these are listed within the system interrupts register (r16), as described in table 63 . the status of the irq inputs can be read at any time from this register or else in response to the interrupt (irq) output being signalled via a gpio pin. individual mask bits can select or deselect different functions from the interrupt controller. these are listed within the system interrupts mask register (r19), as described in table 63. note that the status fields remain valid, even when masked, but the masked bits will not cause the interrupt (irq) output to be asserted. the interrupt (irq) output represents the logical or of all the u nmasked irq inputs. the bits within the system interrupts register (r16) are latching fields and, once they are set, they are not reset until the system interrupts register is read. accordingly, the interrupt (irq) output is not reset until the system interrupts register has been read. note that, if the condition that caused the irq input to be asserted is still valid, then the interrupt (irq) output will remain set even after the system interrupts register has been read. when gpio input is used to trigger an interrupt event, polarity can be set using the gpn_pol bits as described in table 61 . this allows the irq event to be used to indicate a rising or a falling edge of the external logic signal. i f desired, the gpn_int_mode bits can be used to select an interrupt event on bot h the rising and falling edges.
WM8944B 90 rev 4. 3 the gpio inputs to the interrupt controller are de-bounced to avoid false detections. the timeout clock (toclk) is required for this function. when using gpio inputs to the interrupt controller, the toclk must be enabled by setting the toclk_ena and osc_clk_ena bits as described in clocking and sample rates . the interrupt (irq) output can be globally masked by setting the im_irq register. the interrupt is masked by default. the interrupt (irq) output may be configured on any of the gpio pins . see general purpose input / output for details of how to configure gpio pins for interrupt (irq) output. the interrupt control fields are defined in table 63. register address bit label default description r16 (10h) system interrupts (read only) 15 temp_int 0 ther m al interrupt status (read only) 0 = thermal interrupt not set 1 = thermal interrupt set this bit is latched when set; it is cl eared when the register is read. 13 gp2 _int 0 gpio2 interrupt status (read only) 0 = gpio2 interrupt not set 1 = gpio2 interrupt set this bit is latched when set; it is cleared when the register is read. 12 gp1 _int 0 gpio1 interrupt status (read only) 0 = gpio1 interrupt not set 1 = gpio1 interrupt set this bit is latched when set; it is cleared when the register is read. 0 ldo_uv_int 0 ldo undervoltage interrupt (read only) 0 = ldo undervoltage interrupt not set 1 = ldo undervoltage interrupt set thi s bit is latched when set; it is cleared when the register is read. r18 (12h) irq config 0 im_irq 1 irq (gpio output) mask 0 = normal 1 = irq output is masked r19 (13h) system interrupts mask 15 im_temp_int 0 interrupt mask for thermal status 0 = not mas ked 1 = masked 13 im_ gp2 _int 0 interrupt mask for gpio2 0 = not masked 1 = masked 12 im_ gp1 _int 0 interrupt mask for gpio1 0 = not masked 1 = masked 0 im_ldo_uv_in t 0 interrupt mask for ldo undervoltage status 0 = not masked 1 = masked table 63 interrupt control
WM8944B rev 4. 3 91 control interface the WM8944B is controlled by writing to its control registers. readback is available for all registers. the control interface can operate as either a 2- or 3-wire interface: ? 2-wire (i2c) mode uses pins sclk and sda ? 3-wire (spi) mode uses pins cs , sclk and sda readback is provided on the bi-directional pin sda in 2- /3 -wire modes. the device address in 2-wire (i2c) mode is 34h. the WM8944B uses 15-bit register addresses and 16-bit data in all control interface modes. selection of control interface mode the WM8944B control interface can be configured for i2c mode or spi modes using the cif mode/gpio2 pin at power-up. the mode selection is as described in table 65. cif mode/ gpio2 interface format low 2 - wire high 3 - wire table 64 control interface mode selection after the control interface mode has been configured, the mode_gpio register bit should be set in order to latch the selection and to allow gpio functions to be supported on the cif mode/gpio2 pin. after the mode_gpio register bit has been set, the control interface mode selection will remain latched until a software reset or power on reset occurs. see general purpose input / output for details. in 2-wire (i2c) control interface mode, auto-increment mode may be selected. this enables multiple write and multiple read operations to be scheduled faster than is possible with single register operations. the auto-increment option is enabled when the auto_inc register bit is set. this bit is defined in table 65 . auto-increment is enabled by default. in 3-wire (spi) control interface mode, register readback is provided using the bi-directional pin sda . when the sda pin is an output, it may be configured as cmos or as open drain using the spi_od bit. an external pull-up resistor is required if using the open drain output. the control interface configuration bits are described in table 65. regi ster address bit label default description r20 (14h) control interface 2 spi_od 0 sda pin output configuration 0 = sda output is cmos 1 = sda output is open - drain 0 auto_inc 1 enables address auto - increment (applies to 2 - wire / i2c mode only) 0 = disabl ed 1 = enabled table 65 control interface configuration
WM8944B 92 rev 4. 3 2-wire (i2c) control mode in 2-wire mode, the WM8944B is a slave device on the control interface; sclk is a clock input, while sda is a bi-directional data pin. to allow arbitration of multiple slaves (and/or multiple masters) on the same interface, the WM8944B transmits logic 1 by tri-stating the sda pin, rather than pulling it high. an external pull-up resistor is required to pull the sda line high so that the logic 1 can be recognised by the master. in order to allow many devices to share a single 2-wire control bus, every device on the bus has a unique 8-bit device id (this is not the same as the 15-bit address of each register in the WM8944B). the WM8944B device id is 001 1 0100 (34h). the lsb of the device id is the read/write bit; this bit is set to logic 1 for read and logic 0 for write. the WM8944B operates as a slave device only. the controller indicates the start of data transfer with a high to low transition on s da while sclk remains high. this indicates that a device id, register address and data will follow. the WM8944B responds to the start condition and shifts in the next eight bits on sda (8-bit device id including read/write bit, msb first). if the device id received matches the device id of the WM8944B, then the WM8944B responds by pulling sda low on the next clock pulse (ack). if the device id is not recognised or the r/w bit is 1 when operating in write only mode, the WM8944B returns to the idle condition and waits for a new start condition and valid address. if the device id matches the device id of the WM8944B, the data transfer continues as described below. the controller indicates the end of data transfer with a low to high transition on sda while sclk remains high. after receiving a complete address and data sequence the WM8944B returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sda changes while sclk is high), the device returns to the idle condition. the WM8944B supports the following read and write operations: ? single write ? single read ? multiple write using auto-increment ? multiple read using auto-increment the sequence of signals associated with a single register write operation is illustrated in figure 34. figure 34 control interface 2-wire (i2c) register write the sequence of signals associated with a single register read operation is illustrated in figure 35. a9 d7 d1 a15 sda sclk device id data bits b15 C b8 a8 b15 b8 b1 b0 note: the sda pin is used as input for the control register address and data; sda is pulled low by the receiving device to provide the acknowledge (ack) response r/w b9 b7 register address a15 - a8 data bits b7 C b0 start (write) ack ack ack stop ack a1 a7 a0 register address a7 - a0 ack
WM8944B rev 4. 3 93 figure 35 control interface 2-wire (i2c) register read the control interface also supports other register operations, as listed above. the interface protocol for these operations is summarised below. the terminology used in the following figures is detailed in table 66. note that, for multiple write and multiple read operations, the auto-increment option must be enabled. this feature is enabled by default, as noted in table 65. terminology description s start condition sr repeated start a acknowledge (sda low) a not acknowledge (sda high) p stop conditio n r/ w readnotwrite 0 = write 1 = read [white field] data flow from bus master to WM8944B [grey field] data flow from WM8944B to bus master table 66 control interface terminology figure 36 single register write to specified address figure 37 single register read from specified address device id b9 b8 d1 b15 data bits b15 C b8 ack r/w (read) b1 b0 b7 data bits b15 C b8 ack stop ack a9 d7 d1 a15 sda sclk device id device id a8 d7 note: the sda pin is driven by both the master and slave devices in turn to transfer device address, register address, data and ack responses r/w register address a15 C a8 start (write) ack ack rpt start a1 a7 a0 register address a7 C a0 device id s a msbyte address (0) a msbyte data a lsbyte data a p 8 bit device id 8 bits 8 bits 8 bits lsbyte address a 8 bits rw device id sr a p msbyte data (1) lsbyte data a device id s a msbyte address (0) a a a lsbyte address rw rw
WM8944B 94 rev 4. 3 figure 38 multiple register write to specified address using auto-increment figure 39 multiple register read from specified address using auto-increment figure 40 multiple register read from last address using auto-increment multiple write and multiple read operations enable the host processor to access sequential blocks of the data in the WM8944B register map faster than is possible with single register operations. the auto -increment option is enabled when the auto_inc register bit is set. this bit is defined in table 65 . auto-increment is disabled by default. 3-wire (spi) control mode the 3-wire control interface uses the cs , sclk and sda pins. in 3-wire control mode, a control word consists of 32 bits. the first bit is the read/write bit (r/w), which is followed by 15 address bits (a 14 to a0) that determine which control register is accessed. the remaining 16 bits (b15 to b0) are data bits, corresponding to the 16 bits in each control register. in 3-wire mode, every rising edge of sclk clocks in one data bit from the sda pin. the data is latched on the 32 nd falling edge of sclk after 32 bits of data have been clocked into the device. in write operations (r/w=0), all sda bits are driven by the controlling device. in read operations (r/w=1), the sda pin is driven by the controlling device to clock in the register address, after which the wm8 944b drives the sda pin to output the applicable data bits. when the spi_od register bit is set , the WM8944B transmits logic 1 by tri - stating the sda pin, rather than pulling it high. an external pull - up resistor is required to pull the sda line high so th at the logic 1 can be recognised by the master. the 3-wire control mode timing is illustrated in figure 41. device id s a msbyte address (0) a msbyte data 0 a lsbyte data 0 a written to 'register address' a msbyte data n a lsbyte data n a p written to 'register address+n' msbyte data 1 msbyte data n-2 a msbyte data n-1 a lsbyte data n-1 written to 'register address+n-1' lsbyte address a rw sr device id s a msbyte address (0) a device id a (1) read from 'register address' msbyte data 0 lsbyte data 0 a a p msbyte data n lsbyte data n a a a msbyte data n-1 lsbyte data n-1 a a read from 'last register address+n' read from 'last register address+n-1' lsbyte address a rw rw device id a p msbyte data n (1) lsbyte data n a s a a msbyte data 0 lsbyte data 0 a a msbyte data n-1 lsbyte data n-1 a a read from 'last register address' read from 'last register address+n' read from 'last register address+n-1' msbyte data 1 lsbyte data 1 a a read from 'last register address+1' rw
WM8944B rev 4. 3 95 figure 41 3-wire serial control interface power management the wm 8944b has two control registers that allow users to select which functions are active. for minimum power consumption, unused functions should be disabled. to minimise pop or click noise, it is important to enable or disable these functions in the correct order, and to use the signal mute registers as part of a carefully structured control sequence. the power management control registers are described in table 67. register address bit label default description r2 (02h) power manage ment 1 12 inpga_ena 0 input pga enable 0 = disabled 1 = enabled 11 adcr_ena 0 right adc enable 0 = disabled 1 = enabled adcr_ena must be set to 1 when processing right channel data from the digital microphone. 10 adcl_ena 0 left adc enable 0 = disabled 1 = enabled adcl_ena must be set to 1 when processing data from the adc or from the left digital microphone. 4 micb_ena 0 microphone bias enable 0 = disabled 1 = enabled 3 bias_ena 0 master bias enable 0 = disabled 1 = enabled r3 (03h) power manageme nt 2 14 out_ena 0 lineout enable 0 = disabled 1 = enabled 12 spk_pga_ena 0 speaker pga enable 0 = disabled 1 = enabled r/w a14 a13 a12 a2 a1 sda sclk cs 15-bit control register address 16-bit control register data a0 b15 b14 b13 b2 b0 b1
WM8944B 96 rev 4. 3 register address bit label default description 11 spkn_spkvdd _ena 0 spkoutn enable 0 = disabled 1 = enabled note that spkoutn is also controlled by spkn_op_ena. when powering down spkoutn, the spkn_spkvdd_ena bit should be reset first. 10 spkp_spkvdd _ena 0 spkoutp enable 0 = disabled 1 = enabled note that spkoutp is also controlled by spkp_op_ena. when powering down spkoutp, the spkp_spkvdd_ena bit should be reset first 7 spkn_o p_ena 0 spkoutn enable 0 = disabled 1 = enabled note that spkoutn is also controlled by spkn_spkvdd_ena. when powering up spkoutn, the spkn_op_ena bit should be enabled first. 6 spkp_op_ena 0 spkoutp enable 0 = disabled 1 = enabled note that spkoutp is a lso controlled by spkp_spkvdd_ena. when powering up spkoutp, the spkp_op_ena bit should be enabled first 2 spk_mix_ena 0 speaker output mixer enable 0 = disabled 1 = enabled 0 dac_ena 0 dac enable 0 = disabled 1 = enabled dac_ena must be set to 1 when processing data from the dac or digital beep generator. table 67 power management control note: in 2-wire mode in order to achieve the minimum power down current from dbvdd the cif_mode pin should be configured as a gpio pin by setting register r11 (0bh) bit 0 high and configured as an input in register r14 ( 0e h) bit 0 set high. pull-up and pull-down resistors should be disabled in register r14 (0eh) bits 14:13 set to 00.
WM8944B rev 4. 3 97 thermal shutdown the WM8944B incorporates a temperature sensor which detects when the device temperature is within normal limits. the temperature status can be read at any time from the temp_sts bit, as described in table 68 . this bit can be polled at any time, or may output directly on a gpio pin, or may be used to generate interrupt events. the temperature sensor can be configured to shut down the speaker outputs in the event of an overtemperature condition. this is configured using the therr_act register field. register address bit labe l default description r17 (11h) status flags 15 temp_sts 0 thermal sensor status (read only) 0 = normal 1 = overtemperature r42 (2ah) output ctrl 15 therr_act 1 thermal s hutdown enable 0 = d isabled 1 = e nabled when therr_act = 1, then an over temperature condition will cause the speaker outputs to be disabled. table 68 thermal shutdown control note: for minimum power down current the thermal shutdown should be disabled by setting the therr_act bit in register r42 (2ah) bit 15 low. power on reset the WM8944B includes a power-on reset (por) circuit, which is used to reset the digital logic into a default state after power up. the por circuit derives its output from ldo vdd and dcvdd. the internal por signal is asserted low when either ldo vdd or dcvdd are below minimum thresholds. the specific behaviour of the circuit will vary, depending on relative timing of the supply voltages. typical scenarios are illustrated in figure 42 and figure 43. figure 42 power on reset timing C ldovdd enabled first dcvdd v pord_on 0v lo por undefined hi internal por internal por active internal por active device ready ldovdd 0v v pora v pora_off
WM8944B 98 rev 4. 3 figure 43 power on reset timing - dcvdd enabled first the por signal is undefined until ldovdd has exceeded the minimum threshold, v pora once this threshold has been exceeded, por is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. once ldo vdd and dcvdd have both reached their respective power on thresholds, por is released high, all registers are in their default state, and writes to the control interface may take place. note that a minimum power-on reset period, t por , applies even if ldovdd and dcvdd have zero rise time. (this specification is guaranteed by design rather than test.) on power down, por is asserted low when ldovdd or dcvdd falls below their respective power- down thresholds. typical power-on reset parameters for the WM8944B are defined in table 69. symbol description min typ max unit v pora power - on undefined threshold ( ldovdd ) 0.5 v v pora_on power - on threshold ( ldovdd /dbvdd ) 1. 17 v v pora_off power - off threshold ( ldovdd /dbvdd ) 1. 13 v v pord_on power - on threshold (dcvdd) 0. 66 v v pord_off power - off threshold (dcvdd) 0. 64 v t por minimum power - on reset period 10.6 ? table 69 typical power-on reset parameters se parate power-on reset circuits are also implemented on the dbvdd and spkvdd domains. these circuits ensure correct device behaviour whenever these supplies are enabled or disabled. dcvdd 0v ldovdd 0v v pora v pord_off lo por undefined hi internal por internal por active device ready internal por active v pora_on
WM8944B rev 4. 3 99 software reset and device id the WM8944B can be reset by writing to register r0. this is a read-only register, and the contents of r0 will not be affected by writing to this register. the device id can be read back from register r0. the chip revision id can be read back from register 1, as described in table 70. register address bit label default description r0 (00h) software reset/chip id 1 15:0 sw_reset [15:0] 6264h writing to this register resets all registers to their default state. reading from this register will indicate device family id 6264h. r 1 (01h) revision number 3:0 chip_rev [3:0] 0h reading from this register will indicate the revision id. (read only) table 70 chip reset and id
WM8944B 100 rev 4. 3 recommended p ow er - up / power-down sequences in order to minimise output pop and click noise, it is recommended that the WM8944B device is powered-up and powered-down using the control sequences described in table 71 and table 72 respectively. the power-up sequence described here includes enabling the dacs and output drivers; note that additional configuration will be required to enable the required internal signal paths. the sequences noted here are provided as guidance only; each sequence will require to be adjusted to the particular appli cation requirements. description label register [bits] turn on external supplies and wait for the supply voltages to settle. reset registers to default state (software reset) . sw_reset r0 (00h) [15:0] enable speaker and line discharge bits . enable vmi d to speaker and line outputs . spkp_disch = 1 spkn_disch = 1 line_disch = 1 spkp_vmid_op_ena = 1 spkn_vmid_op_ena = 1 line_vmid_op_ena = 1 r42 (2ah) [6] r42 (2ah) [7] r42 (2ah) [4] r42 (2ah) [12] r42 (2ah) [13] r42 (2ah) [10] enable vmi d fast start and st art up bias. select start - up bias and set vmid soft start for start - up ramp . vmid_fast_start = 1 startup_bias_ena = 1 bias_src = 1 vmid_ramp[1:0] = 01 r7 (07h) [11] r7 (07h) [8] r7 (07h) [7] r7 (07h) [6:5] if using vmid as the reference voltage for the ld o then select vmid fast start or set to 0 if using the bandgap as the reference voltage for ldo. select ldo start - up bias and enable ldo. delay 300ms for ldo to settle. ldo_ena = 1 ldo_ref_sel_fast = 1 ldo_bias_src = 1 r53 (35h) [15] r53 (35h) [14] r53 (35 h) [5] enable vmid buffer and master bias. set vmid_sel[1:0] for fast start - up. bias_ena = 1 vmid_buf_ena = 1 vmid_sel[1:0] = 11 r2 (02h) [3] r2 (02h) [2] r2 (02h) [1:0] disable speaker and line discharge bits. spkp_disch = 0 spkn_disch = 0 line_disch = 0 r42 (2ah) [6] r42 (2ah) [7] r42 (2ah) [4] enable speaker outputs and speaker pga and lineout output as required. spk_mix_ena = 1 dac_ena = 1 spkn_op_ena = 1 spkp_op_ena = 1 spk_pga_ena = 1 out_ena = 1 r3 (03h) [2] r3 (03h) [0] r3 (03h) [7] r3 (03h) [6] r3 (03h) [12] r3 (03h) [14] enable power to speaker driver (must be done after enabling the speaker outputs). spkn_spkvdd_ena = 1 spkp_spkvdd_ena = 1 r3 (03h) [11] r3 (03h) [10] enable vmid. delay 50ms to allow vmid to settle. vmid_ena = 1 r7 (07h) [4] set ldo and vmid for normal operation. ldo_ref_sel_fast = 0 ldo_bias_src = 0 vmid_fast_start = 0 startup_bias_ena = 0 vmid_sel = 01 r53 (35h) [14] r53 (35h) [5] r7 (07h) [11] r7 (07h) [8] r2 (02h) [1:0] un - mute outputs as required. table 71 recommended power-up sequence
WM8944B rev 4. 3 101 description label register [bits] mute speaker pga and dac . spk_pga_mute = 1 spk_vol = 00h dac_mute = 1 dac_vol = 0 r 47 (2fh) [6] r47 (2fh) [5:0] r23 (17h) [8] r23 (17h) [7:0] select ldo for fast start - up . ldo _ref_sel_fast = 1 ldo_bias_src = 1 r53 (35h) [14] r53 (35h) [5] select vmid for fast start - up . vmid_sel = 11 vmid_fast_start =1 bias_src = 1 vmid_ramp = 01 r2 (02h) [1:0] r7 (07h) [11] r7 (07h) [7] r7 (07h) [6:5] disable vmid . delay 500ms for vmid to dis charge . vmid_ena = 0 r7 (07h) [4] discharge the speaker and line outputs . delay 50ms for outputs to discharge . spkp_disch = 1 spkn_disch = 1 line_disch = 1 r42 (2ah) [7] r42 (2ah) [6] r42 (2ah) [4] mute the speaker and line outputs . lineout_mute = 1 spkn _op_mute = 1 spkp_op_mute = 1 r 42 (2ah) [8] r03 (03h) [9] r03 (03h) [8] disable power to speaker drivers (must be done before disabling the speaker outputs) . spk n _spkvdd_ena = 0 spk p _spkvdd_ena = 0 r3 (03h) [11] r3 (03h) [10] disable speaker outputs . spk n_op_ena = 0 spkp_op_ena = 0 r3 (03h) [7] r3 (03h) [6] reset registers to default state (software reset). sw_reset r0 (00h) [15:0] turn off external power supply voltages . table 72 recommended power-down sequence
WM8944B 102 rev 4. 3 register map reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r0 (0h) software reset/chip id 1 sw_reset[15:0] 62 64 h r1 (1h) chip id 2 (read only) 0 0 0 0 0 0 0 0 0 0 0 0 chip_rev[3:0] 0000h r2 (2h) power management 1 0 0 0 inp pga _ e na adcr_ ena adc l _ ena 0 0 dmic_ ena 0 spk _ l ow vmid _ ena micb_ ena bias_ ena vmid_ buf _ e na vmid_sel[1:0] 0000h r3 (3h) power management 2 0 out _ e na 0 spk _ p ga _ en a spkn _ spkvd d _ ena spkp _ spkvd d _ ena spkn _ op _ m ute spkp _ op _ m ute spkn _ op _ en a spkp _ op _ en a 0 spk_m ix _ mu te 0 spk_m ix _ en a 0 dac _ e na 0310h r4 (4h) audio interface dacdata _ pul l [ 1:0] frame _ pull [ 1:0] bclk _ pull [ 1:0] adcr _ src adc l _ src 0 dac _ s rc bclk_i nv lrclk _inv wl [ 1:0] fmt [ 1:0] 020ah r5 (5h) companding control adc_d ac _ lo op 0 0 0 0 0 0 0 0 0 loopb ack 0 dac_c omp dac_c ompm o de adc_c omp adc_c ompm ode 0000h r6 (6h) clock gen control osc_c lk _ en a mclk _ pull [ 1:0] clk out _ s el clkout _ div [ 1:0] sys clk _ e na sys clk _ s rc sysclk_div [ 2:0] toclk _ena bclk_div [ 2:0] mstr 0106h r7 (7h) additional control syscl k_rat e 0 0 0 vmid_ fast_ start vm id_ ref _ s el vmid_ ctrl start up _ bi as_en a bias_ src vmid _ ramp [ 1:0] vmid_ ena sr [ 3:0] 800dh r8 (8h) fll control 1 0 0 0 fll_clk_ref_ div [ 1:0] fll_outdiv [ 2:0] fll_ctrl_rate [ 2:0] fll_fratio [ 2:0] fll _ f rac fll _ e na 0102h r9 (9h) fll control 2 fll_k [ 15:0] 3127h r10 (ah) fll control 3 0 fll_n [ 9:0] 0 fll_gain [ 3:0] 0100h r11 (bh) gpio config 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mode _gpio 0000h r13 (dh) gpio1 control gp1 _ d ir gp1 _pull [ 1:0] gp1 _ i nt _ m ode 0 gp1 _ p ol 0 0 0 0 gp 1 _ l vl 0 gp1 _fn [ 3:0] 8000h r14 (eh) gpio 2 con trol gp2 _ d ir gp2 _pull [ 1:0] gp2 _ i nt _ m ode 0 gp2 _ p ol 0 0 0 0 gp2 _ l vl 0 gp2 _fn [ 3:0] c000h r16 (10h) system interrupts (read only) temp_ int 0 gp2 _ i nt gp1 _ i nt 0 0 0 0 0 0 0 0 0 0 0 ldo _ u v _ int 0000h r17 (11h) status flags (read only) temp_ sts 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ldo _ u v _ sts 0000h r18 (12h) irq config 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 im _ irq 0001h r19 (13h) system interrupts mask im _ te mp _ in t 0 im _ gp 2 _ int im _ gp 1 _ int 0 0 0 0 0 0 0 0 0 0 0 im _ ld o _ uv _ int 0000h r20 (14h) control interface 0 0 0 0 0 0 0 0 0 0 0 0 0 spi _ o d 0 auto_ inc 0001h r21 (15h) dac control 1 0 0 0 0 0 0 0 0 0 0 0 dac _ a utom ute 0 0 0 dac_d at inv 0 0 10h r22 (16h) dac control 2 0 0 0 0 0 0 0 0 0 0 0 dac _ v ol _ ra mp 0 0 0 dac _ s b _ flt 0010h r23 (17h) dac digital vol 0 0 0 0 0 0 0 dac_ mute dac_vol [ 7 :0] 0 1 c0h r25 (19h) adc control 1 0 0 0 0 0 0 0 adc_ mute all 0 0 0 0 0 0 adcr_ dat inv adc l _dat inv 0100h
WM8944B rev 4. 3 103 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r26 (1ah) adc control 2 0 0 0 0 0 0 0 0 0 adc_h pf_mo de adc_hpf _ sr [ 1:0] adc_hpf_cut [ 2:0] adc_h pf 0021h r27 (1bh) left adc digital vol 0 0 0 adc _ v u 0 0 0 adc l _ mute adc l _vol [ 7:0] 0 0c0h r28 (1ch) right adc digital vol 0 0 0 adc _ v u 0 0 0 adcr _ mute adcr_vol [ 7:0] 00c0h r29 (1dh) drc control 1 0 0 0 0 0 0 0 drc_n g _ ena drc_e na 0 0 0 1 drc_ qr drc_a nti clip 1 000fh r30 (1eh) drc control 2 0 0 0 drc_ng_min gain [ 3:0] 0 0 0 1 drc_mingain [ 2:0] drc_max gain [ 1:0] 0c25h r31 (1fh) drc control 3 0 0 0 0 0 0 1 1 drc_atk [ 3:0] drc_dcy [ 3:0] 0342h r32 (20h) drc control 4 0 0 0 drc_knee2_ip [ 4:0] drc_knee_ip [ 5:0] 0 0 0000h r33 (21h) drc control 5 0 0 drc_k nee2_ op _ en a drc_knee2_op [ 4:0] drc_knee_op [ 4:0] drc_hi_comp [ 2:0] 0003h r34 (22h) drc control 6 0 0 0 0 0 0 0 0 0 0 0 0 drc_qr _ thr [ 1:0] drc_qr _ dcy [ 1:0] 0000h r35 (23h) drc control 7 0 0 0 0 0 0 drc_ng _ exp [ 1:0] drc_lo_comp [ 2:0] drc_init [ 4:0] 0000h r36 (2 4h) drc status (read only) drc_gain [ 15:0] 0000h r37 (25h) beep control 1 0 0 0 0 0 0 0 0 0 beep_gain [ 3:0] beep_rate [ 1:0] beep_ ena 0002h r38 (26h) video buffer 0 0 0 0 0 0 0 0 vb _ en a vb_qb oost vb _ ga in vb_disoff [ 2:0] vb_pd vb_cl amp 001ch r39 (27h) inp ut ctrl 0 0 0 0 0 0 aux _ t o_n_i npga 0 0 micb_ lvl 0 0 0 0 p_pga _ sel [ 1:0] 0001h r40 (28h) i nput pga gain ctrl 0 0 0 0 0 0 0 0 in pga _zc in pga _mute in pga_vol [ 5:0] 0050h r42 (2ah) output ctrl therr _act 0 spkn _ vmid_ op_en a spkp _ vmid_ op_en a 0 line_v mid_o p _ ena 0 line_ mute spkn _ disch spk p _ disch 0 line_ disch 0 0 spk _ v roi line_v roi 8 1 00h r43 (2bh) spk mixer control1 0 0 0 0 0 aux diff_t o _ pga in1 _ t o _ pga aux _ t o _ spk p pga _ t o _ spk p byp _ t o _ pga mdac _to _ p ga 0 dac _ t o _ pga 0 0 aux _ t o _ pga 0000h r44 (2ch) spk mixer control2 0 0 0 0 0 0 in1 _ t o _ spk n 0 pga _ t o _ spk n 0 0 0 0 0 0 0 0000h r45 (2dh) spk mixer control3 0 0 0 0 0 aux diff_t o _ pga _ atte n in1 _ t o _ pga _ atte n aux _ t o _ spk p _ att en pga _ t o _ spk p _ att en byp _ t o _ pga _ atte n 0 0 dac _ t o _ pga _ atte n 0 0 aux _ t o _ pga _ atte n 0000h r46 (2eh) spk mixer control4 0 0 0 0 0 0 in1 _ t o _ spk n _ att en 0 pga _ t o _ spk n _att en 0 0 0 0 0 0 0 0000h r47 (2fh) spk volume ctrl 0 0 0 0 0 0 0 0 spk _ z c spk _ p ga_m ute spk_vol [ 5:0] 0079h r49 (31h) line mixer control 1 0 0 0 0 0 aux diff_t o_out in1 _ t o_out 0 0 byp _ t o _ out mdac _to_o u t 0 dac _ t o _ out 0 0 aux _ t o _ out 0000h
WM8944B 104 rev 4. 3 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r51 (33h) line l mixer control 2 0 0 0 0 0 aux diff_t o _ out _ atte n in1 _ t o _ out _ atte n 0 0 byp _ t o _ out _ atte n 0 0 dac _ t o _ out _ atte n 0 0 aux _ t o _ out _ atte n 0000h r53 (35h) ldo ldo _ e na ldo _ r ef _ se l _ fas t ldo _ r ef _ se l ldo_o pflt 0 0 0 0 0 0 ldo _ b ias_s rc ldo_vsel [ 4:0] 0007h r54 (36h) bandgap bg _ en a 0 0 0 0 0 0 0 0 0 0 bg_vsel [ 4:0] 000ah r64 (40h) se config selection 0 0 0 0 0 0 0 0 0 0 0 0 se_config [ 3:0] 0000h r65 (41h) se1_lhpf_config 0 0 0 0 0 0 0 0 0 0 se1_l hpf_r _sign se1_l hpf_l _sign 0 0 se1_l hpf_r _ena se1_l hpf_l _ena 0000h r66 (42h) se1_lhpf _l se1_lhpf _l [ 15:0] 0000h r67 (43h) se1_lhpf_r se1_lhpf_r [ 15:0] 0000h r68 (44h) se1_3d_config 0 0 0 0 0 0 se1_3 d_r_s ign se1_3 d_l_si gn se1_3 d_lhp f_r_e na se1_3 d_lhp f_l_e na se1_3 d_r_l hpf_s ig n se1_3 d_l_l hpf_s ign 0 0 se1_3 d_r_e na se1_3 d_l_e na 0000h r69 (45h) se1_3d_l 0 0 se1_3d_l _ delay [ 2:0] se1_3d_l _ cutoff [ 2:0] se1_3d_l_cgain [ 3:0] se1_3d_l_fgain [ 3:0] 0408h r70 (46h) se1_3d_r 0 0 se1_3d_r _ delay [ 2:0] se1_3d_r _ cutoff [ 2:0] se1_3d_r_cgain [ 3:0] se1_3d_r_fgain [ 3:0] 0408h r71 (47h) se1_notch _ confi g 0 0 0 0 0 0 0 0 0 0 0 0 0 0 se1_n otch_ r_ena se1_n otch_ l_ena 0000h r72 (48h) se1_notch_a10 se1_notch_a10 [ 15:0] 0000h r73 (49h) se1_notch_a11 se1_notch_a11 [ 15:0] 0000h r74 (4ah) se1_notch_a20 se1_notch_a20 [ 15:0] 0000h r75 (4bh) se1_notch_a21 se1_notch_a21 [ 15:0] 0000h r76 (4ch) se1_notch_a30 se1_notch_a30 [ 15:0] 0000h r77 (4dh) se1_notch_a31 se1_notch_a31 [ 15:0] 0000h r78 (4eh) se1_notch_a40 se1_notch_a40 [ 15:0] 0000h r79 (4fh) se1_notch_ a41 se1_notch_a41 [ 15:0] 0000h r80 (50h) se1_notch_a50 se1_notch_a50 [ 15:0] 0000h r81 (51h) se1_notch_a51 se1_notch_a51 [ 15:0] 0000h r82 (52h) se1_notch_m10 se1_notch_m10 [ 15:0] 0000h r83 (53h) se1_notch_m11 se1_notch_m11 [ 15:0] 1000h r84 (54h) se1_no tch_m20 se1_notch_m20 [ 15:0] 0000h r85 (55h) se1_notch_m21 se1_notch_m21 [ 15:0] 1000h r86 (56h) se1_notch_m30 se1_notch_m30 [ 15:0] 0000h r87 (57h) se1_notch_m31 se1_notch_m31 [ 15:0] 1000h r88 (58h) se1_notch_m40 se1_notch_m40 [ 15:0] 0000h r89 (59h) se 1_notch_m41 se1_notch_m41 [ 15:0] 1000h r90 (5ah) se1_notch_m50 se1_notch_m50 [ 15:0] 0000h r91 (5bh) se1_notch_m51 se1_notch_m51 [ 15:0] 1000h r92 (5ch) se1_df1_config 0 0 0 0 0 0 0 0 0 0 0 0 0 0 se1 _ d f1 _ r_ ena se1 _ d f1 _ l_ ena 0000h r93 (5dh) se1_df1_l0 se1 _df1_l0 [ 15:0] 1000h r94 (5eh) se1_df1_l1 se1_df1_l1 [ 15:0] 0000h r95 (5fh) se1_df1_l2 se1_df1_l2 [ 15:0] 0000h r96 (60h) se1_df1_r0 se1_df1_r0 [ 15:0] 1000h r97 (61h) se1_df1_r1 se1_df1_r1 [ 15:0] 0000h
WM8944B rev 4. 3 105 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r98 (62h) se1_df1_r2 se1_df1_r2 [ 15:0] 0000h r99 (63h) se2_hpf_config 0 0 0 0 0 0 0 0 0 0 0 0 0 0 se2_h pf_ r _ ena se2_h pf_l_ ena 0000h r100 (64h) se2_retune _ conf ig 0 0 0 0 0 0 0 0 0 0 0 0 0 0 se2_r etune _r_en a se2_r etune _ l_ en a 0000h r101 (65h) se2_retune_c0 se2_retune_c0 [ 15:0] 1000h r102 (66h) se2_retune _c1 se2_retune_c1 [ 15:0] 0000h r103 (67h) se2_retune_c2 se2_retune_c2 [ 15:0] 0000h r104 (68h) se2_retune_c3 se2_retune_c3 [ 15:0] 0000h r105 (69h) se2_retune_c4 se2_retune_c4 [ 15:0] 0000h r106 (6ah) se2_retune_c5 se2_retune_c5 [ 15:0] 0000h r107 (6bh) s e2_retune_c6 se2_retune_c6 [ 15:0] 0000h r108 (6ch) se2_retune_c7 se2_retune_c7 [ 15:0] 0000h r109 (6dh) se2_retune_c8 se2_retune_c8 [ 15:0] 0000h r110 (6eh) se2_retune_c9 se2_retune_c9 [ 15:0] 0000h r111 (6fh) se2_retune_c10 se2_retune_c10 [ 15:0] 0000h r 112 (70h) se2_retune_c11 se2_retune_c11 [ 15:0] 0000h r113 (71h) se2_retune_c12 se2_retune_c12 [ 15:0] 0000h r114 (72h) se2_retune_c13 se2_retune_c13 [ 15:0] 0000h r115 (73h) se2_retune_c14 se2_retune_c14 [ 15:0] 0000h r116 (74h) se2_retune_c15 se2_retune_ c15 [ 15:0] 0000h r117 (75h) se2_retune_c16 se2_retune_c16 [ 15:0] 0000h r118 (76h) se2_retune_c17 se2_retune_c17 [ 15:0] 0000h r119 (77h) se2_retune_c18 se2_retune_c18 [ 15:0] 0000h r120 (78h) se2_retune_c19 se2_retune_c19 [ 15:0] 0000h r121 (79h) se2_ret une_c20 se2_retune_c20 [ 15:0] 0000h r122 (7ah) se2_retune_c21 se2_retune_c21 [ 15:0] 0000h r123 (7bh) se2_retune_c22 se2_retune_c22 [ 15:0] 0000h r124 (7ch) se2_retune_c23 se2_retune_c23 [ 15:0] 0000h r125 (7dh) se2_retune_c24 se2_retune_c24 [ 15:0] 0000h r126 (7eh) se2_retune_c25 se2_retune_c25 [ 15:0] 0000h r127 (7fh) se2_retune_c26 se2_retune_c26 [ 15:0] 0000h r128 (80h) se2_retune_c27 se2_retune_c27 [ 15:0] 0000h r129 (81h) se2_retune_c28 se2_retune_c28 [ 15:0] 0000h r130 (82h) se2_retune_c29 se2_retun e_c29 [ 15:0] 0000h r131 (83h) se2_retune_c30 se2_retune_c30 [ 15:0] 0000h r132 (84h) se2_retune_c31 se2_retune_c31 [ 15:0] 0000h r133 (85h) se2_5beq_config 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 se2 _ 5 beq _ l _ ena 0000h r134 (86h) se2_5beq_l10g 0 0 0 se2_5beq_l1g [ 4: 0] 0 0 0 se2_5beq_l0g [ 4:0] 0c0ch r135 (87h) se2_5beq_l32g 0 0 0 se2_5beq_l3g [ 4:0] 0 0 0 se2_5beq_l2g [ 4:0] 0c0ch r136 (88h) se2_5beq_l4g 0 0 0 0 0 0 0 0 0 0 0 se2_5beq_l4g [ 4:0] 000ch r137 (89h) se2_5beq_l0p se2_5beq_l0p [ 15:0] 00d8h r138 (8ah) se2_5 beq_l0a se2_5beq_l0a [ 15:0] 0fcah r139 (8bh) se2_5beq_l0b se2_5beq_l0b [ 15:0] 0400h r140 (8ch) se2_5beq_l1p se2_5beq_l1p [ 15:0] 01c5h r141 (8dh) se2_5beq_l1a se2_5beq_l1a [ 15:0] 1eb5h r142 (8eh) se2_5beq_l1b se2_5beq_l1b [ 15:0] f145h r143 (8fh) se2_5b eq_l1c se2_5beq_l1c [ 15:0] 0b75h
WM8944B 106 rev 4. 3 reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r144 (90h) se2_5beq_l2p se2_5beq_l2p [ 15:0] 0558h r145 (91h) se2_5beq_l2a se2_5beq_l2a [ 15:0] 1c58h r146 (92h) se2_5beq_l2b se2_5beq_l2b [ 15:0] f373h r147 (93h) se2_5beq_l2c se2_5beq_l2c [ 15:0] 0a54h r148 (94h) se2_5be q_l3p se2_5beq_l3p [ 15:0] 1103h r149 (95h) se2_5beq_l3a se2_5beq_l3a [ 15:0] 168eh r150 (96h) se2_5beq_l3b se2_5beq_l3b [ 15:0] f829h r151 (97h) se2_5beq_l3c se2_5beq_l3c [ 15:0] 07adh r152 (98h) se2_5beq_l4p se2_5beq_l4p [ 15:0] 4000h r153 (99h) se2_5beq _l4a se2_5beq_l4a [ 15:0] 0564h r154 (9ah) se2_5beq_l4b se2_5beq_l4b [ 15:0] 0559h r155 (9bh) se2_5beq_r10g 0 0 0 se2_5beq_r1g [ 4:0] 0 0 0 se2_5beq_r0g [ 4:0] 0c0ch r156 (9ch) se2_5beq_r32g 0 0 0 se2_5beq_r3g [ 4:0] 0 0 0 se2_5beq_r2g [ 4:0] 0c0ch r157 (9dh ) se2_5beq_r4g 0 0 0 0 0 0 0 0 0 0 0 se2_5beq_r4g [ 4:0] 000ch r158 (9eh) se2_5beq_r0p se2_5beq_r0p [ 15:0] 00d8h r159 (9fh) se2_5beq_r0a se2_5beq_r0a [ 15:0] 0fcah r160 (a0h) se2_5beq_r0b se2_5beq_r0b [ 15:0] 0400h r161 (a1h) se2_5beq_r1p se2_5beq_r1p [ 15 :0] 01c5h r162 (a2h) se2_5beq_r1a se2_5beq_r1a [ 15:0] 1eb5h r163 (a3h) se2_5beq_r1b se2_5beq_r1b [ 15:0] f145h r164 (a4h) se2_5beq_r1c se2_5beq_r1c [ 15:0] 0b75h r165 (a5h) se2_5beq_r2p se2_5beq_r2p [ 15:0] 0558h r166 (a6h) se2_5beq_r2a se2_5beq_r2a [ 15: 0] 1c58h r167 (a7h) se2_5beq_r2b se2_5beq_r2b [ 15:0] f373h r168 (a8h) se2_5beq_r2c se2_5beq_r2c [ 15:0] 0a54h r169 (a9h) se2_5beq_r3p se2_5beq_r3p [ 15:0] 1103h r170 ( aah ) se2_5beq_r3a se2_5beq_r3a [ 15:0] 168eh r171 ( abh ) se2_5beq_r3b se2_5beq_r3b [ 15:0 ] f829h r172 ( ach ) se2_5beq_r3c se2_5beq_r3c [ 15:0] 07a d h r173 ( adh ) se2_5beq_r4p se2_5beq_r4p [ 15:0] 4000h r174 ( aeh ) se2_5beq_r4a se2_5beq_r4a [ 15:0] 0564h r175 ( afh ) se2_5beq_r4b se2_5beq_r4b [ 15:0] 0559h
WM8944B rev 4. 3 107 register bits by add ress the complete register map is shown below. the detailed description can be found in the relevant text of the device description. register address bit label default description refer to r0 (00h) software reset/chip id 1 15:0 sw_reset [ 15:0] 0110_0010 _ 0110 _ 010 0 writing to th is register resets all registers to their default state. reading from this register will indicate device family id 62 64 h. register 00h software reset/chip id 1 register address bit label default description refer to r1 (01h) chip id 2 (read only) 3:0 c hip_rev [ 3:0] 0000 reading from this register will indicate the revision id (read only). register 01h chip id 2 register address bit label default description refer to r2 (02h) power manage - ment 1 12 inpga_ena 0 input pga enable 0 = disabled 1 = enable d 11 adcr_ena 0 right adc enable 0 = disabled 1 = enabled adcr_ena must be set to 1 when processing right channel data from the digital microphone. 10 adcl_ena 0 left adc enable 0 = disabled 1 = enabled adcl_ena must be set to 1 when processing data from the adc or digital microphone. 7 dmic_ena 0 enables digital microphone mode 0 = audio dsp input is from adc 1 = audio dsp input is from digital microphone interface when dmic_ena = 0, the digital microphone clock (dmicclk) is held low. 5 spk_ lo wvmid_ ena 0 selects 0.9v midrail voltage for speaker output drivers 0 = disabled 1 = enabled this bit should be enabled if spkvdd = 1.8v 4 micb_ena 0 microphone bias enable 0 = disabled 1 = enabled 3 bias_ena 0 master bias enable 0 = disabled 1 = en abled 2 vmid_buf _ ena 0 vmid buffer enable. (the buffered vmid may be applied to disabled input and output pins.) 0 = disabled 1 = enabled 1:0 vmid_sel [ 1:0] 00 vmid divider enable and select
WM8944B 108 rev 4. 3 register address bit label default description refer to 00 = vmid disabled (for off mode) 01 = 2 x 50k divider (fo r normal operation) 10 = 2 x 250k divider (for low power standby) 11 = 2 x 5k divider (for fast start - up) register 02h power management 1 register address bit label default description refer to r3 (03h) power manage - ment 2 14 out_ena 0 lineout enable 0 = disabled 1 = enabled 12 spk_pga _ ena 0 speaker pga enable 0 = disabled 1 = enabled 11 spkn _ spkvdd_ena 0 spkoutn enable 0 = disabled 1 = enabled note that spkoutn is also controlled by spkn _op_ena. when powering down spkoutn , the spkn _spkvdd_ena b it should be reset first. 10 spkp _ spkvdd_ena 0 spkoutp enable 0 = disabled 1 = enabled note that spkoutp is also controlled by spkp _op_ena. when powering down spkoutp , the spkp _spkvdd_ena bit should be reset first 9 spkn _op _ mute 1 spkoutn output mu te 0 = disable mute 1 = enable mute 8 spkp _op _ mute 1 spkoutp output mute 0 = disable mute 1 = enable mute 7 spkn _op _ ena 0 spkoutn enable 0 = disabled 1 = enabled note that spkoutn is also controlled by spkn _spkvdd_ena. when powering up spkoutn , the spkn _op_ena bit should be enabled first. 6 spk p _op _ ena 0 spkoutp enable 0 = disabled 1 = enabled note that spkoutp is also controlled by spkp _spkvdd_ena. when powering up spkoutp , the spkp _op_ena bit should be enabled first 4 spk_mix _ mute 1 speake r pga mixer mute 0 = disable mute 1 = enable mute 2 spk_mix_ena 0 s peaker output mixer enable 0 = disabled 1 = enabled 0 dac_ena 0 dac enable 0 = disabled 1 = enabled
WM8944B rev 4. 3 109 register address bit label default description refer to dac_ena must be set to 1 when processing data from the dac or digital beep generato r. register 03h power management 2 register address bit label default description refer to r4 (04h) audio interface 15:14 dacdata _ pull [ 1:0] 00 dacdat pull - up / pull - down enable 00 = no pull - up or pull - down 01 = pull - down 10 = pull - up 11 = reserved 13:12 frame_pull [1:0] 00 lrclk pull - up / pull - down enable 00 = no pull - up or pull - down 01 = pull - down 10 = pull - up 11 = reserved 11:10 bclk_pull [1:0] 00 bclk pull - up / pull - down enable 00 = no pull - up or pull - down 01 = pull - down 10 = pull - up 11 = res erved 9 adcr_src 1 right digital audio interface source 0 = left adc data is output on right channel 1 = right adc data is output on right channel 8 adc l _src 0 left digital audio interface source 0 = left adc data is output on left channel 1 = right adc data is output on left channel 6 dac_src 0 dac data source select 0 = dac outputs left channel interface data 1 = dac outputs right channel interface data 5 bclk_inv 0 bclk invert 0 = bclk not inverted 1 = bclk inverted 4 lrclk_inv 0 lrclk po larity / dsp mode a - b select. l eft and i2s modes C C see companding for the selection of 8
WM8944B 110 rev 4. 3 register address bit label default description refer to 01 = left justified 10 = i2s format 11 = dsp/pcm mode register 04h audio interface register address bit label default description refer to r5 (05h) companding control 15 adc_dac _ loopback digital audio interface loopback function 0 = no loopback 1 = loo pback enabled (adc data is fed directly into dac data input). 5 loopback 0 digital loopback function 0 = no loopback 1 = loopback enabled (dacdat input is fed through the dsp core to the adcdat output). 3 dac_comp 0 dac companding enable 0 = disabled 1 = enabled 2 dac_ compmode 0 dac companding mode 0 = - law 1 = a - law 1 adc_comp 0 adc companding enable 0 = disabled 1 = enabled 0 adc_ compmode 0 adc companding mode 0 = - law 1 = a - law register 05h companding control register address bit la bel default description refer to r6 (06h) clock gen control 15 osc_clk _ ena 0 oscillator enable 0 = disabled 1 = enabled this needs to be set when a timeout clock is required for gpio input detection 14:13 mclk_pull [1:0] 00 mclk pull - up / pull - down en able 00 = no pull - up or pull - down 01 = pull - down 10 = pull - up 11 = reserved 12 clkout_sel 0 clkout source select 0 = sysclk 1 = fll or mclk (set by sysclk_src register) 11:10 clkout_div [1:0] 00 clkout clock divider 00 = divide by 1 01 = divide by 2 10 = divide by 4 11 = divide by 8
WM8944B rev 4. 3 111 register address bit la bel default description refer to 9 sysclk_ena 0 sysclk enable 0 = disabled 1 = enabled 8 sysclk_src 1 sysclk source select 0 = mclk 1 = fll output 7:5 sysclk_div [ 2:0] 000 sysclk clock divider (sets the scaling for either the mclk or fll clock ou tput, depending on sysclk_src) 000 = divide by 1 001 = divide by 1.5 010 = divide by 2 011 = divide by 3 100 = divide by 4 101 = divide by 6 110 = divide by 8 111 = divide by 12 4 toclk_ena 0 toclk enabled (enables timeout clock for gpio level detection ) 0 = disabled 1 = enabled 3:1 bclk_div [ 2:0] 011 bclk frequency (master mode) 000 = sysclk 001 = sysclk / 2 010 = sysclk / 4 011 = sysclk / 8 100 = sysclk / 16 101 = sysclk / 32 110 = reserved 111 = reserved 0 mstr 0 digital audio interface mode sel ect 0 = slave mode 1 = master mode register 06h clock gen control register address bit label default description refer to .r7 (07h) additional control 15 sysclk_ rate 1 selects the sysclk / fs ratio 0 = sysclk = 256 x fs 1 = sysclk = 512 x fs 11 vmid_fast _ start 0 vmid (fast - start) enable 0 = disabled 1 = enabled 10 vmid_ref _ sel 0 vmid source select 0 = ldo supply (ldovdd) 1 = ldo output (ldovout) 9 vmid_ctrl 0 vmid ratio control sets the ratio of vmid to the source selected by vmid_ref_sel 0 = 5/11 1 = 1/2 8 startup _ 0 start - up bias enable
WM8944B 112 rev 4. 3 register address bit label default description refer to bias_ena 0 = disabled 1 = enabled 7 bias_src 0 bias source select 0 = master bias 1 = start - up bias 6:5 vmid_ramp [ 1:0] 00 vmid soft start enable / slew rate control 00 = disabled 01 = fast soft start 10 = normal soft start 11 = slow soft start 4 vmid_ena 0 vmid enable 0 = disabled 1 = enabled 3:0 sr [ 3:0] 1101 audio sample rate select 0011 = 8khz 0100 = 11.025khz 0101 = 12khz 0111 = 16khz 1000 = 22.05khz 1001 = 24khz 1011 = 32khz 1100 = 44 .1khz 1101 = 48khz register 07h additional control register address bit label default description refer to r8 (08h) fll control 1 12:11 fll_clk _ ref_ div [ 1:0] 00 fll clock reference divider 00 = mclk / 1 01 = mclk / 2 10 = mclk / 4 11 = mclk / 8 mclk (or other input reference) must be divided down to <=13.5mhz. for lower power operation, the reference clock can be divided down further if desired. 10:8 fll_outdiv [ 2:0] 001 fout clock divider 000 = 2 001 = 4 010 = 8 011 = 16 100 = 32 101 = 64 110 = 6 111 = 12 (fout = fvco / fll_outdiv) 7:5 fll_ctrl _ rate [ 2:0] 000 frequency of the fll control block 000 = fvco / 1 (recommended value) 001 = fvco / 2 010 = fvco / 3
WM8944B rev 4. 3 113 register address bit label default description refer to 011 = fvco / 4 100 = fvco / 5 101 = fvco / 6 110 = fvco / 7 111 = fvco / 8 rec ommended that this register is not changed from default. 4:2 fll_fratio [ 2:0] 000 fvco clock divider 000 = 1 001 = 2 010 = 4 011 = 8 1xx = 16 000 recommended for fref > 1mhz 100 recommended for fref < 16khz 011 recommended for all other cases 1 fll_ frac 1 fractional enable 0 = integer mode 1 = fractional mode integer mode offers reduced power consumption. fractional mode offers best fll performance, provided also that n.k is a non - integer value. 0 fll_ena 0 fll enable 0 = disabled 1 = enabled register 08h fll control 1 register address bit label default description refer to r9 (09h) fll control 2 15:0 fll_k [ 15:0] 0011_0001 _0010_011 1 fractional multiply for fref (msb = 0.5) register 09h fll control 2 register address bit label default desc ription refer to r10 (0ah) fll control 3 14:5 fll_n [ 9:0] 00_0000_1 000 integer multiply for fref (lsb = 1) 3:0 fll_gain [ 3:0] 0 0 00 gain applied to error 0000 = x 1 (recommended value) 0001 = x 2 0010 = x 4 0011 = x 8 0100 = x 16 0101 = x 32 0110 = x 64 0111 = x 128 1000 = x 256
WM8944B 114 rev 4. 3 register address bit label default desc ription refer to recommended that this register is not changed from default. register 0ah fll control 3 register address bit label default description refer to r11 (0bh) gpio config 0 mode_gpio 0 cifmode/ gpio2 pin configuration 0 = pin conf igured as cifmode 1 = pin configured as gpio2 note - when this bit is set to 1, it is latched and cannot be reset until power - off or software reset. register 0bh gpio config register address bit label default description refer to r13 (0dh) gpio1 contro l 15 gp1 _dir 1 gpio1 pin direction 0 = output 1 = input 14:13 gp1 _pull [ 1:0] 00 gpio1 pull - up / pull - down enable 00 = no pull - up or pull - down 01 = pull - down 10 = pull - up 11 = reserved 12 gp1 _int _ mode 0 gpio1 interrupt mode 0 = gpio interrupt is risi ng edge triggered (if gp1 _pol=0) or falling edge triggered (if gp1 _pol =1) 1 = gpio interrupt is triggered on rising and falling edges 10 gp1 _pol 0 gpio1 polarity select 0 = non - inverted 1 = inverted 5 gp1 _lvl 0 gpio1 level. write to this bit to set a gpio output. read from this bit to read gpio input level. when gp1 _pol is set, the register contains the opposite logic level to the external pin. 3:0 gp1 _fn [ 3:0] 0000 gpio1 pin function 0000 = logic level input 0001 = edge detection input 0010 = clk out output 0011 = interupt (irq) output 0100 = reserved 0101 = reserved 0110 = reserved 0111 = temperature flag output 1000 = reserved 1001 = dmicclk output 1010 = logic level output 1011 = ldo_uv output 1100 = reserved 1101 = reserved 1110 = reserved 11 11 = reserved table 62
WM8944B rev 4. 3 115 register 0dh gpio1 control register address bit label default description refer to r14 (0eh) gpio2 control 15 gp2 _dir 1 gpio2 pin direction 0 = output 1 = input 14:13 gp2 _pull [ 1:0] 10 gpio2 pull - up / pull - down enable 00 = no pull - up or pull - down 01 = pull - down 10 = pull - up 11 = reserved 12 gp2 _int _ mode 0 gpio2 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp2 _pol=0) or falling edge triggered (if gp2 _pol =1) 1 = gpio interrupt is tr iggered on rising and falling edges 10 gp2 _pol 0 gpio2 polarity select 0 = non - inverted 1 = inverted 5 gp 2 _lvl 0 gpio2 level. write to this bit to set a gpio output. read from this bit to read gpio input level. when gp2 _pol is set, the register conta ins the opposite logic level to the external pin. 3:0 gp2 _fn [ 3:0] 0000 gpio2 pin function 0000 = logic level input 0001 = edge detection input 0010 = clkout output 0011 = interupt (irq) output 0100 = reserved 0101 = reserved 0110 = reserved 0111 = temp erature flag output 1000 = reserved 1001 = dmicclk output 1010 = logic level output 1011 = ldo_uv output 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved table 62 register 0eh gpio2 control register address bit label default description refer to r16 (10h) system interrupts (read only) 15 temp_int 0 thermal interrupt status (read only) 0 = thermal interrupt not set 1 = thermal interrupt set this bit is latched when set; it is cleared when the register is read. 13 gp2 _int 0 gpio2 interrupt status (read only) 0 = gpio2 interrupt not set 1 = gpio2 interrupt set this bit is latched when set; it is cleared when the register
WM8944B 116 rev 4. 3 register address bit label default description refer to is read. 12 gp1 _int 0 gpio1 interrupt status (read only) 0 = gpio 1 interrupt not set 1 = g pio1 interrupt set this bit is latched when set; it is cleared when the register is read. 0 ldo_uv_int 0 ldo undervoltage interrupt (read only) 0 = ldo undervoltage interrupt not set 1 = ldo undervoltage interrupt set this bit is latched when set; it is cleared when the register is read. register 10h system interrupts register address bit label default description refer to r17 (11h) status flags (read only) 15 temp_sts 0 thermal sensor status (read only) 0 = normal 1 = overtemperature 0 ldo_uv_sts 0 ldo undervoltage status (read only) 0 = normal 1 = undervoltage register 11h status flags register address bit label default description refer to r18 (12h) irq config 0 im_irq 1 irq (gpio output) mask 0 = normal 1 = irq output is masked register 12 h irq config register address bit label default description refer to r19 (13h) system interrupts mask 15 im_temp_int 0 interrupt mask for thermal status 0 = not masked 1 = masked 13 im_ gp2 _int 0 interrupt mask for gpio2 0 = not masked 1 = masked 12 im_ gp1 _int 0 interrupt mask for gpio1 0 = not masked 1 = masked 0 im_ldo_uv _ int 0 interrupt mask for ldo undervoltage status 0 = not masked 1 = masked register 13h system interrupts mask register address bit label default description refer to r20 (14h) 2 spi_od 0 selects cmos or open - drain output (in 3 - wire mode only)
WM8944B rev 4. 3 117 register address bit label default description refer to control interface 0 = sda is normal push cmos 1 = sda is open - d rain 0 auto_inc 1 enables address auto - increment (applies to 2 - wire / i2c mode only) 0 = disabled 1 = enabled register 14h control interface register address bit label default description refer to r21 (15h) dac control 1 4 dac_ automute 1 dac auto - mute control 0 = disabled 1 = enabled 0 dac_datinv 0 dac data invert 0 = dac output not inverted 1 = dac output inve rted register 15h dac control 1 register address bit label default description refer to r22 (16h) dac control 2 4 dac_vol _ ramp 1 dac volume ramp control 0 = disabled 1 = enabled 0 dac_sb_flt 0 selects dac filter characteristics 0 = normal mode 1 = sloping stopband mode register 16h dac control 2 register address bit label default description refer to r23 (17h) dac digital vol 8 dac_mute 1 dac digital mute 0 = disable mute 1 = enable mute 7:0 dac_vol [ 7:0] 1100_0000 dac digital volume 0000_00 00 = mute 0000_0001 = - 71.625db 0000_0010 = - 71.250db register 17h left dac digital vol register address bit label default description refer to r25 (19h) adc control 1 8 adc_ muteall 1 adc digital mute for all channels 0 = disable mute 1 = enable mute on all channels
WM8944B 118 rev 4. 3 register address bit label default description refer to 1 adcr _ datinv 0 right adc data invert 0 = right adc output not inverted 1 = right adc output inverted 0 adcl _ datinv 0 left adc data invert 0 = adc output not inverted 1 = adc output inverted register 19h adc control 1 register address bit label default description refer to r26 (1ah) adc control 2 6 adc_hpf _ mode 0 sets the adc hpf response (1 st or 2 nd order). 0 = audio mode (1 st order) 1 = application mode (2 nd order) 5:4 adc_hpf _ sr [ 1:0] 10 adc hpf sample frequency range 00 = 8khz to 12khz 01 = 16khz to 24khz 10 = 32khz to 48khz 11 = 88khz to 96khz 3:1 adc_hpf _ cut [ 2 :0] 000 high pass filter configuration. see table 11 for cut - off frequencies at all supported sample rates. table 11 0 adc_hpf 1 adc digital high pass filter enable 0 = disabled 1 = enabled register 1ah adc control 2 register address bit label default descriptio n refer to r27 (1bh) left adc digital vol 12 adc_vu 0 adc volume update writing a 1 to this bit enables the left adc volume to be updated 8 adc l _mute 0 left adc digital mute 0 = disable mute 1 = enable mute 7:0 adc l _vol [ 7:0] 1100_0000 left adc digi tal volume 0000_0000 = mute 0000_0001 = - 71.625db 0000_0010 = - 71.250db register 1bh left adc digital vol register address bit label default description refer to r28 (1ch) rig ht adc 12 adc_vu 0 adc volume update writing a 1 to this bit will cause left and right adc volume
WM8944B rev 4. 3 119 register address bit label default description refer to digital vol to be updated simultaneously 8 adcr_mute 0 right adc digital mute 0 = disable mute 1 = enable mute 7:0 adcr_vol [ 7:0] 1100_0000 right adc di gital volume 0000_0000 = mute 0000_0001 = - 71.625db 0000_0010 = - 71.250db register 1ch right adc digital vol register address bit label default description refer to r29 (1dh) drc control 1 8 drc_ng_ena 0 drc noise gate enable 0 = disabled 1 = enabled 7 drc_ena 0 drc enable 0 = disabled 1 = enabled 2 drc_qr 1 drc quick - release enable 0 = disabled 1 = enabled 1 drc_ anticlip 1 drc anti - clip enable 0 = disabled 1 = enabl ed register 1dh drc control 1 register address bit label default description refer to r30 (1eh) drc control 2 12:9 drc_ng_ mingain [ 3:0] 0110 minimum gain the drc can use to attenuate audio signals when the noise gate is active. 0000 = - 36db 0001 = - 30db 0010 = - 24db 0011 = - 18db 0100 = - 12db 0101 = - 6db 0110 = 0db 0111 = 6db 1000 = 12db 1001 = 18db 1010 = 24db 1011 = 30db 1100 = 36db 1101 to 1111 = reserved
WM8944B 120 rev 4. 3 register address bit label default description refer to 4:2 drc_mingain [ 2:0] 001 minimum gain the drc can use to attenuate audio signals 000 = 0 db 001 = - 12db (default) 010 = - 18db 011 = - 24db 100 = - 36db 101 = reserved 11x = reserved 1:0 drc_ maxgain [ 1:0] 01 maximum gain the drc can use to boost audio signals (db) 00 = 12db 01 = 18db 10 = 24db 11 = 36db register 1eh drc control 2 register address bit label default description refer to r31 (1fh) drc control 3 7:4 drc_atk [ 3:0] 0100 a ttack rate relative to the input signal (seconds/6db) 0000 = reserved 0001 = 181us 0010 = 363us 0011 = 726us 0100 = 1.45ms 0101 = 2.9ms 0110 = 5.8ms 0111 = 11 .6ms 1000 = 23.2ms 1001 = 46.4ms 1010 = 92.8ms 1011 = 185.6ms 1100 - 1111 = reserved 3:0 drc_dcy [ 3:0] 0010 d ecay rate relative to the input signal (seconds/6db) 0000 = 186ms 0001 = 372ms 0010 = 743ms 0011 = 1.49s 0100 = 2.97s 0101 = 5.94s 0110 = 11.89s 0 111 = 23.78s 1000 = 47.56s 1001 - 1111 = reserved register 1fh drc control 3 register address bit label default description refer to r32 (20h) drc control 4 12:8 drc_knee2 _ ip [ 4:0] 0_0000 input signal level at the noise gate threshold knee2.
WM8944B rev 4. 3 121 register address bit label default description refer to ( input signal level at the compressor knee. ( register 20h drc control 4 register address bit label default description refer to r33 (21h) drc control 5 13 drc_knee2_o p_ena 0 drc_knee2_op enable 0 = disabled 1 = enabled 12:8 drc_knee2_o p [ 4:0] 0_0000 output signal at the noise gate threshold knee2. ( output signal at the compressor knee. ( register 21h drc control 5 register address bit label default description refer to r34 (22h) drc control 6 3:2 drc_qr_thr [ 1:0] 00 drc quick - release threshold (crest factor in db) 00 = 12db 01 = 18db
WM8944B 122 rev 4. 3 register address bit label default description refer to 10 = 24db 11 = 30db 1:0 drc_qr_dcy [ 1:0] 00 drc quick - release decay rate (seconds/6db) 00 = 0.725ms 01 = 1.45ms 10 = 5.8ms 11 = reserved register 22h drc control 6 register address bit label default description refer to r35 (23h) drc control 7 9:8 drc_ng_exp [ 1:0] 00 noise gate slope 00 = 1 (no expansion) 01 = 2 10 = 4 11 = 8 7:5 drc_lo _ com p [ 2:0] 000 compressor slope (lower region) 000 = 1 (n o compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 = reserved 11x = reserved 4:0 drc_init 00000 iinitial value at drc startup 00000 = 0db 00001 = - 3.75db ( register 23h drc control 7 register address bit label default description refer to r36 (24h) drc status (read only) 15:0 drc_gain [ 15:0] 0000_0000 _0000_000 0 drc gain value (read only) . this is the drc gain, expressed as a voltage multiplier. fixed point coding, msb = 64. the first 7 bits are the integer port ion; the remaining bits are the fractional part. register 24h drc status register address bit label default description refer to r37 (25h) beep control 1 6:3 beep_gain [ 3:0] 0000 digital beep volume control 0000 = mute 0001 = - 83db 0010 = - 77db (6db
WM8944B rev 4. 3 123 register address bit label default description refer to 2:1 beep_rate [ 1:0] 01 beep waveform control 00 = reserved 01 = 1khz 10 = 2khz 11 = 4khz 0 beep_ena 0 digital beep enable 0 = disabled 1 = enabled note that the dac and associated signal path needs to be enabled when using the digi tal beep. register 25h beep control 1 register address bit label default description refer to r38 (26h) video buffer 7 vb_ena 0 video buffer enable 0 = disabled 1 = enabled 6 vb_qboost 0 video buffer filter q - boost control 0 = disabled 1 = enabled 5 vb_gain 0 video buffer gain 0 = 0db (=6db unloaded) 1 = 6db (=12db unloaded) 4:2 vb_disoff [ 2:0] 111 video buffer dc offset control 000 = reserved 001 = 40mv offset 010 = reserved 011 = 20mv offset 100 = reserved 101 = reserved 110 = reserved 111 = 0mv offset note - the specified offset applies to the 0db gain setting (vb_gain=0). when 6db gain is selected, the dc offset is doubled. 1 vb_pd 0 video buffer pull - down 0 = pull - down disabled 1 = pull - down enabled 0 vb_clamp 0 enable the clamp betwe en the video input and ground 0 = no clamp 1 = video buffer input is clamped to ground register 26h video buffer register address bit label default description refer to r39 (27h) input ctrl 9 aux_to_n _ inpga 0 input pga inverting input select 0 = conne cted to vmid 1 = connected to aux
WM8944B 124 rev 4. 3 register address bit label default description refer to 6 micb_lvl 0 microphone bias voltage control 0 = 0.9 x ldovout 1 = 0.65 x ldovout 1:0 p_pga_sel [ 1:0] 01 input pga non - inverting input select 00 = reserved 01 = connected to in1/dmicdat 10 = connected to aux 11 = res erved register 27h input ctrl register address bit label default description refer to r40 (28h) input pga gain ctrl 7 inpga_zc 0 input pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 6 in pga_mute 1 input pga mu te 0 = disable mute 1 = enable mute 5:0 in pga_vol [ 5:0] 01_0000 input pga volume 00_0000 = - 12db 00_0001 = - 11.25db register 28h input pga gain ctrl register address bit label defa ult description refer to r42 (2ah) output ctrl 15 therr_act 1 thermal shutdown enable 0 = disabled 1 = enabled when therr_act = 1, then an over temperature condition will cause the speaker outputs to be disabled. 13 spkn _vmid_o p_ena 0 buffered vmid to spkoutn enable 0 = disabled 1 = enabled 12 spkp _vmid_o p_ena 0 buffered vmid to spkoutp enable 0 = disabled 1 = enabled 10 line_vmid _ op_ena 0 buffered vmid to lineout enable 0 = disabled 1 = enabled 8 line_mute 1 lineout output mute 0 = disable mu te 1 = enable mute 7 spk n _disch 0 discharges spkoutn output via approx 550 ohm resistor 0 = not active 1 = actively discharging spkout n
WM8944B rev 4. 3 125 register address bit label defa ult description refer to 6 spkp _disch 0 discharges spkoutp output via approx 550 ohm resistor 0 = not active 1 = actively discharging spkou tp 4 line_disch 0 discharges lineout output via approx 550 ohm resistor 0 = not active 1 = actively discharging lineout 1 spk_vroi 0 buffered vref to spkoutp / spkoutn resistance (disabled outputs) 0 = approx 20k ohms 1 = approx 1k4 ohms 0 line_vr oi 0 buffered vref to lineout resistance (disabled output) 0 = approx 20k ohms 1 = approx 1k1 ohms register 2ah output ctrl register address bit label default description refer to r43 (2bh) spk mixer control1 10 auxdiff_to_p ga 0 differential aux/in1 to speaker pga mixer select 0 = disabled 1 = enabled 9 in1_to_pga 0 in1 to speaker pga mixer select 0 = disabled 1 = enabled 8 aux_to_ spkp 0 aux to spkoutp select 0 = disabled 1 = enabled 7 pga_to_ spkp 0 speaker pga mixer to spkoutp select 0 = d isabled 1 = enabled 6 byp_to_pga 0 input pga (adc bypass) to speaker pga mixer select 0 = disabled 1 = enabled 5 mdac_to _ pga 0 inverted dac to speaker pga mixer select 0 = disabled 1 = enabled 3 dac_to_pga 0 dac to speaker pga mixer select 0 = di sabled 1 = enabled 0 aux_to_pga 0 aux to speaker pga mixer select 0 = disabled 1 = enabled register 2bh spk mixer control1
WM8944B 126 rev 4. 3 register address bit label default description refer to r44 (2ch) spk mixer control2 9 in1_to_spkn 0 in1 to spkoutn select 0 = disabled 1 = enabled 7 pga_to_ spkn 0 speaker pga mixer to spkoutn select 0 = disabled 1 = enabled register 2ch spk mixer control2 register address bit label default description refer to r45 (2dh) spk mixer control3 10 auxdiff_to_p ga_atten 0 differ ential aux/in1 to speaker pga mixer attenuation 0 = 0db 1 = - 6db attenuation 9 in1_to_pga_a tten 0 in1 to speaker pga mixer attenuation 0 = 0db 1 = - 6db attenuation 8 aux_to_ spkp_atten 0 aux to spkoutp attenuation 0 = 0db 1 = - 6db attenuation 7 pg a_to_ spkp_atten 0 speaker pga mixer to spkoutp attenuation 0 = 0db 1 = - 6db attenuation 6 byp_to_pga_ atten 0 input pga (adc bypass) to speaker pga mixer attenuation 0 = 0db 1 = - 6db attenuation 3 dac_to_pga_ atten 0 dac to speaker pga mixer attenuati on 0 = 0db 1 = - 6db attenuation 0 aux_to_pga_ atten 0 aux to speaker pga mixer attenuation 0 = 0db 1 = - 6db attenuation register 2dh spk mixer control3 register address bit label default description refer to r46 (2eh) spk mixer control4 9 in1_to_spkn _ atten 0 in1 to spkoutn attenuation 0 = 0db 1 = - 6db attenuation 7 pga_to_ spkn_atten 0 speaker pga mixer to spkoutn attenuation 0 = 0db 1 = - 6db attenuation register 2eh spk mixer control4 register address bit label default description refer to r47 (2fh) spk volume ctrl 7 spk_zc 0 speaker pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only
WM8944B rev 4. 3 127 register address bit label default description refer to 6 spk_pga_ mute 1 speaker pga mute 0 = disable mute 1 = enable mute 5:0 spk_vol [ 5:0] 11_1001 speaker pga volume 00_0000 = - 57db gain 00_0001 = - 56db register 2fh spk volume ctrl register address bit label default description refer to r49 (31h) line mixer control 1 10 auxdiff_to_o ut 0 differential aux /in1 to line output mixer select 0 = disabled 1 = enabled 9 in1_to_out 0 in1 to line output mixer select 0 = disabled 1 = enabled 6 byp_to_out 0 input pga (adc bypass) to line output mixer select 0 = disabled 1 = enabled 5 mdac_to_ out 0 inverted dac to line output mixer select 0 = disabled 1 = enabled 3 dac_to_out 0 dac to line output mixer select 0 = disabled 1 = enabled 0 aux_to_out 0 aux to line output mixer select 0 = disabled 1 = enabled register 31h line mixer control 1 register add ress bit label default description refer to r51 (33h) line mixer control 2 10 auxdiff_to_o ut_atten 0 differential aux/in1 to line output mixer attenuation 0 = 0db 1 = - 6db attenuation 9 in1_to_out_a tten 0 in1 to line output mixer attenuation 0 = 0db 1 = - 6db attenuation 6 byp_to_out_ atten 0 input pga (adc bypass) to line output mixer attenuation 0 = 0db 1 = - 6db attenuation 3 dac_to_out_ atten 0 dac to line output mixer attenuation 0 = 0db 1 = - 6db attenuation 0 aux_to_out_ atten 0 aux to line ou tput mixer attenuation 0 = 0db
WM8944B 128 rev 4. 3 register add ress bit label default description refer to 1 = - 6db attenuation register 33h line mixer control 2 register address bit label default description refer to r53 (35h) ldo 15 ldo_ena 0 ldo enable 0 = disabled 1 = enabled 14 ldo_ref_ sel_fast 0 ldo voltage reference select 0 = vmid (normal) 1 = vmid (fast start) this field is only effective when ldo_ref_sel = 0 13 ldo_ref_ sel 0 ldo voltage reference select 0 = vmid 1 = bandgap 12 ldo_opflt 0 ldo output float 0 = disabled (output discharged when disabled) 1 = e nabled (output floats when disabled) 5 ldo_ bias_ src 0 bias source select 0 = master bias 1 = start - up bias (fast) 4:0 ldo_vsel [ 4:0] 0_0111 ldo voltage select (sets the ldo output as a ratio of the selected voltage reference. the voltage reference i s set by ldo_ref_sel.) 00111 = vref x 1.97 (default) table 38 register 35h ldo register address bit label default description refer to r54 (36h) bandgap 15 bg_ena 0 bandgap reference control 0 = disabled 1 = enabled 4:0 bg_v sel [ 4:0] 0_1010 bandgap voltage select (sets the bnadgap voltage) 00000 = 1.200v 26.7mv steps table 38 register 36h bandgap register address bit label defau lt description refer to r64 (40h) se config selection 3:0 se_config [ 3:0] 0000 dsp configuration mode select 0000 = record mode 0001 = playback mode 0010 = dsp general mode 1 0011 = dsp general mode 2
WM8944B rev 4. 3 129 register 40h se config selection register address b it label default description refer to r65 (41h) se1_lhpf_ config 5 se1_lhpf_r_s ign 0 se1_lhpf_r_sign 0 : sum internal result (lpf) 1 : sub internal result (hpf) 4 se1_lhpf_l_s ign 0 se1_lhpf_l_sign 0 : sum internal result (lpf) 1 : sub internal result (h pf) 1 se1_lhpf_r_e na 0 se1 right channel low - pass / high - pass filter enable 0 = disabled 1 = enabled 0 se1_lhpf_l_e na 0 se1 left channel low - pass / high - pass filter enable 0 = disabled 1 = enabled register 41h se1_lhpf_config register address bit label default description refer to r66 (42h) se1_lhpf 15:0 se1_lhpf _l [ 15:0] 0000_0000 _0000_000 0 se1_lhpf left coefficent register 42h se1_lhpf register address bit label default description refer to r67 (43h) se1_lhpf_ r 15:0 se1_lhpf_r [ 15:0] 0000_00 00 _0000_000 0 se1_lhpf right channel coefficent register 43h se1_lhpf_r register address bit label default description refer to r68 (44h) se1_3dcon fig 9 se1_3d_r _sign 0 se1_3d_r_sign 0 : add cross path values 1 : sub cross path values 8 se1_3d_l _si gn 0 se1_3d_l_sign 0 : add cross path values 1 : sub cross path values 7 se1_3d_lhpf_ r_ena 0 se1_3d_lhpf_r_ena : 0 : r channel disabled (bypass coeffs applied) 1 : r channel enabled (bank coeffs applied) 6 se1_3d_lhpf_ l_ena 0 se1_3d_lhpf_l_ena : 0 : l channel disabled (bypass coeffs applied) 1 : l channel enabled (bank coeffs applied) 5 se1_3d_r_ lhpf_sign 0 se1_3d_r_lhpf_sign 0 : sum internal result (lpf) 1 : sub internal result (hpf) 4 se1_3d_l_ lhpf_sign 0 se1_3d_l_lhpf_sign 0 : sum internal result (lpf)
WM8944B 130 rev 4. 3 register address bit label default description refer to 1 : sub internal result (hpf) 1 se1_3d_r_ ena 0 se1 right channel 3d stereo enhancement filter enable 0 = disabled 1 = enabled 0 se1_3d_l_ ena 0 se1 left channel 3d stereo enhancement filter enable 0 = disabled 1 = enabled register 44h se1_3d_config register address bit label default description refer to r69 (45h) se1_3d_l 13:11 se1_3d_l_ delay [ 2:0] 000 sets the number of delay samples: 0000 = 0 0001 = 1 0010 = 2 0011 = 3 0100 = 4 10:8 se1_3d_l_ cutoff [ 2:0] 100 cut off frequency 0000 = 50hz 0001 = 100hz 0010 = 200hz 0011 = 400 hz 0100 = 1khz 0101 = 2khz 0110 = 4khz 0111 = 10khz 1000 to 1111 = reserved 7:4 se1_3d_l_ cgain [ 3:0] 0000 se1 3d left channel cross gain setting 0000 = - 12db 0001 = - 10.5db . . register 45h se1_3d_l register address bit label default description refer to r70 (46h) se1_3d_r 13:1 1 se1_3d_r_ delay [ 2:0] 000 sets the number of delay samples: 0000 = 0 0001 = 1 0010 = 2 0011 = 3 0100 = 4 10:8 se1_3d_r_ 100 cut off frequency
WM8944B rev 4. 3 131 register address bit label default description refer to cutoff [ 2:0] 0000 = 50hz 0001 = 100hz 0010 = 200hz 0011 = 400 hz 0100 = 1khz 0101 = 2khz 0110 = 4khz 0111 = 1 0khz 1000 to 1111 = reserved 7:4 se1_3d_r_ cgain [ 3:0] 0000 se1 3d right channel cross gain setting 0000 = - 12db 0001 = - 10.5db . . register 46h se1_3d_r register address bit label default description refer to r71 (47h) se1_ notch_ config 1 se1_notch_r _ena 0 se1 right channel notch filters enable 0 = disabled 1 = enabled 0 se1_notch_l _ena 0 se1 notch filters enable 0 = disabled 1 = enabled register 47h se1_notch_config register address bit label default description refer to r72 (48h) se1_notch _a10 15:0 se1_notch_a 10 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for sig nal enhancement 1 (se1) notch filter register 48h se1_notch_a10 register address bit label default description refer to r73 (49h) se1_notch _a11 15:0 se1_notch_a 11 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filte r register 49h se1_notch_a11
WM8944B 132 rev 4. 3 register address bit label default description refer to r74 (4ah) se1_notch _a20 15:0 se1_notch_a 20 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 4ah se1_notch_a20 reg ister address bit label default description refer to r75 (4bh) se1_notch _a21 15:0 se1_notch_a 21 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 4bh se1_notch_a21 register address bit label default des cription refer to r76 (4ch) se1_notch _a30 15:0 se1_notch_a 30 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 4ch se1_notch_a30 register address bit label default description refer to r77 (4dh) se1_no tch _a31 15:0 se1_notch_a 31 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 4dh se1_notch_a31 register address bit label default description refer to r78 (4eh) se1_notch _a40 15:0 se1_notch_a 40 [ 15:0] 0 000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 4eh se1_notch_a40 register address bit label default description refer to r79 (4fh) se1_notch _a41 15:0 se1_notch_a 41 [ 15:0] 0000_0000 _0000_000 0 filter coefficie nts for signal enhancement 1 (se1) notch filter register 4fh se1_notch_a41 register address bit label default description refer to r80 (50h) se1_notch _a50 15:0 se1_notch_a 50 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 50h se1_notch_a50
WM8944B rev 4. 3 133 register address bit label default description refer to r81 (51h) se1_notch _a51 15:0 se1_notch_a 51 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 51h se1_notch_a51 register address bit label default description refer to r82 (52h) se1_notch _m10 15:0 se1_notch_m 10 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 52h se1_notch_m10 register address bit label default description refer to r83 (53h) se1_notch _m11 15:0 se1_notch_m 11 [ 15:0] 0001_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 53h se1_notch_m11 register address bit label default description refer to r84 ( 54h) se1_notch _m20 15:0 se1_notch_m 20 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 54h se1_notch_m20 register address bit label default description refer to r85 (55h) se1_notch _m21 15:0 se1_notch_m 21 [ 15:0] 0001_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 55h se1_notch_m21 register address bit label default description refer to r86 (56h) se1_notch _m30 15:0 se1_notch_m 30 [ 15:0] 0000_0000 _0000_000 0 filte r coefficients for signal enhancement 1 (se1) notch filter register 56h se1_notch_m30 register address bit label default description refer to r87 (57h) se1_notch _m31 15:0 se1_notch_m 31 [ 15:0] 0001_0000 _0000_000 0 filter coefficients for signal enhanceme nt 1 (se1) notch filter register 57h se1_notch_m31
WM8944B 134 rev 4. 3 register address bit label default description refer to r88 (58h) se1_notch _m40 15:0 se1_notch_m 40 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 58h se1_notch_m40 register address bit label default description refer to r89 (59h) se1_notch _m41 15:0 se1_notch_m 41 [ 15:0] 0001_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 59h se1_notch_m41 register address bit label default description refer to r90 (5ah) se1_notch _m50 15:0 se1_notch_m 50 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 5ah se1_notch_m50 register address bit label default description refe r to r91 (5bh) se1_notch _m51 15:0 se1_notch_m 51 [ 15:0] 0001_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) notch filter register 5bh se1_notch_m51 register address bit label default description refer to r92 (5ch) se1_df1_ config 1 s e1_df1_r _ena 0 se1 right channel df1 filter enable 0 = disabled 1 = enabled 0 se1_df1_l _ena 0 se1 left channel df1 filter enable 0 = disabled 1 = enabled register 5ch se1_df1_config register address bit label default description refer to r93 (5dh) se1_df1_ l0 15:0 se1_df1_l0 [ 15:0] 0001_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) channel df1 filter register 5dh se1_df1_l0 register address bit label default description refer to r94 (5eh) se1_df1_ 15:0 se1_df1_l1 [ 15:0] 0 000_0000 _0000_000 filter coefficients for signal enhancement 1 (se1) channel df1 filter
WM8944B rev 4. 3 135 register address bit label default description refer to l1 0 register 5eh se1_df1_l1 register address bit label default description refer to r95 (5fh) se1_df1_ l2 15:0 se1_df1_l2 [ 15:0] 0000_0000 _0000_000 0 filter coefficient s for signal enhancement 1 (se1) channel df1 filter register 5fh se1_df1_l2 register address bit label default description refer to r96 (60h) se1_df1_ r0 15:0 se1_df1_r0 [ 15:0] 0001_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) righ t channel df1 filter register 60h se1_df1_r0 register address bit label default description refer to r97 (61h) se1_df1_ r1 15:0 se1_df1_r1 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) right channel df1 filter register 61h se1_df1_r1 register address bit label default description refer to r98 (62h) se1_df1_ r2 15:0 se1_df1_r2 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 1 (se1) right channel df1 filter register 62h se1_df1_r2 register addre ss bit label default description refer to r99 (63h) se2_hpf_ config 1 se2_hpf_r _ena 0 se2 right channel high - pass filter enable 0 = disabled 1 = enabled 0 se2_hpf_l _ena 0 se2 left channel high - pass filter enable 0 = disabled 1 = enabled register 63 h se2_hpf_config register address bit label default description refer to r100 (64h) se2_retun e_config 1 se2_retuner __ena 0 se2 right channel retune filter enable 0 = disabled 1 = enabled
WM8944B 136 rev 4. 3 register address bit label default description refer to 0 se2_retunel __ena 0 se2 left channel retune filter enable 0 = d isabled 1 = enabled register 64h se2_retune_config register address bit label default description refer to r101 (65h) se2_retun e_c0 15:0 se2_retune_ c0 [ 15:0] 0001_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 65h se2_retune_c0 register address bit label default description refer to r102 (66h) se2_retun e_c1 15:0 se2_retune_ c1 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 66h se2_retune_c1 register add ress bit label default description refer to r103 (67h) se2_retun e_c2 15:0 se2_retune_ c2 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 67h se2_retune_c2 register address bit label default descriptio n refer to r104 (68h) se2_retun e_c3 15:0 se2_retune_ c3 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 68h se2_retune_c3 register address bit label default description refer to r105 (69h) se2_retun e _c4 15:0 se2_retune_ c4 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 69h se2_retune_c4 register address bit label default description refer to r106 (6ah) se2_retun e_c5 15:0 se2_retune_ c5 [ 15:0] 000 0_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 6ah se2_retune_c5
WM8944B rev 4. 3 137 register address bit label default description refer to r107 (6bh) se2_retun e_c6 15:0 se2_retune_ c6 [ 15:0] 0000_0000 _0000_000 0 filter coefficie nts for signal enhancement 2 (se2) retune filter register 6bh se2_retune_c6 register address bit label default description refer to r108 (6ch) se2_retun e_c7 15:0 se2_retune_ c7 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2 ) retune filter register 6ch se2_retune_c7 register address bit label default description refer to r109 (6dh) se2_retun e_c8 15:0 se2_retune_ c8 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 6dh se 2_retune_c8 register address bit label default description refer to r110 (6eh) se2_retun e_c9 15:0 se2_retune_ c9 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 6eh se2_retune_c9 register address bit label default description refer to r111 (6fh) se2_retun e_c10 15:0 se2_retune_ c10 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 6fh se2_retune_c10 register address bit label default description ref er to r112 (70h) se2_retun e_c11 15:0 se2_retune_ c11 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 70h se2_retune_c11 register address bit label default description refer to r113 (71h) se2_retun e_c 12 15:0 se2_retune_ c12 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 71h se2_retune_c12
WM8944B 138 rev 4. 3 register address bit label default description refer to r114 (72h) se2_retun e_c13 15:0 se2_retune_ c13 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 72h se2_retune_c13 register address bit label default description refer to r115 (73h) se2_retun e_c14 15:0 se2_retune_ c14 [ 15:0] 0000_0000 _0000_000 0 filter coe fficients for signal enhancement 2 (se2) retune filter register 73h se2_retune_c14 register address bit label default description refer to r116 (74h) se2_retun e_c15 15:0 se2_retune_ c15 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhanceme nt 2 (se2) retune filter register 74h se2_retune_c15 register address bit label default description refer to r117 (75h) se2_retun e_c16 15:0 se2_retune_ c16 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter reg ister 75h se2_retune_c16 register address bit label default description refer to r118 (76h) se2_retun e_c17 15:0 se2_retune_ c17 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 76h se2_retune_c17 regi ster address bit label default description refer to r119 (77h) se2_retun e_c18 15:0 se2_retune_ c18 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 77h se2_retune_c18 register address bit label default description refer to r120 (78h) se2_retun e_c19 15:0 se2_retune_ c19 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 78h se2_retune_c19
WM8944B rev 4. 3 139 register address bit label default description refer to r121 (7 9h) se2_retun e_c20 15:0 se2_retune_ c20 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 79h se2_retune_c20 register address bit label default description refer to r122 (7ah) se2_retun e_c21 15:0 se2_re tune_ c21 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 7ah se2_retune_c21 register address bit label default description refer to r123 (7bh) se2_retun e_c22 15:0 se2_retune_ c22 [ 15:0] 0000_0000 _0000 _000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 7bh se2_retune_c22 register address bit label default description refer to r124 (7ch) se2_retun e_c23 15:0 se2_retune_ c23 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 7ch se2_retune_c23 register address bit label default description refer to r125 (7dh) se2_retun e_c24 15:0 se2_retune_ c24 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) ret une filter register 7dh se2_retune_c24 register address bit label default description refer to r126 (7eh) se2_retun e_c25 15:0 se2_retune_ c25 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 7eh se2_retune_c25 register address bit label default description refer to r127 (7fh) se2_retun e_c26 15:0 se2_retune_ c26 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 7fh se2_retune_c26
WM8944B 140 rev 4. 3 register address b it label default description refer to r128 (80h) se2_retun e_c27 15:0 se2_retune_ c27 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 80h se2_retune_c27 register address bit label default description r efer to r129 (81h) se2_retun e_c28 15:0 se2_retune_ c28 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 81h se2_retune_c28 register address bit label default description refer to r130 (82h) se2_retun e _c29 15:0 se2_retune_ c29 [ 15:0] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 82h se2_retune_c29 register address bit label default description refer to r131 (83h) se2_retun e_c30 15:0 se2_retune_ c30 [ 15:0 ] 0000_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) retune filter register 83h se2_retune_c30 register address bit label default description refer to r132 (84h) se2_retun e_c31 15:0 se2_retune_ c31 [ 15:0] 0000_0000 _0000_000 0 filter c oefficients for signal enhancement 2 (se2) retune filter register 84h se2_retune_c31 register address bit label default description refer to r133 (85h) se2_5beq_ config 0 se2_5beq_l_e na 0 se2 left channel 5 - band eq enable 0 = disabled 1 = enabled register 85h se2_5beq_config register address bit label default description refer to r134 (86h) se2_5beq_ l10g 12:8 se2_5beq_ l1g [ 4:0] 0_1100 left channel filter gain1 00000 : - 12db 00001 : - 12db 00010 : - 10db
WM8944B rev 4. 3 141 register address bit label default description refer to 00011 : - 9db 00100 : - 8db 00101 : - 7db 00110 : - 6db 00111 : - 5db 01000 : - 4db 01001 : - 3db 01010 : - 2db 01011 : - 1db 01100 : 0db 01101 : 1db 01110 : 2db 01111 : 3db 10000 : 4db 10001 : 5db 10010 : 6db 10011 : 7db 10100 : 8db 10101 : 9db 10110 : 10db 10111 : 11db 11000 : 12db 11001 to 11111 : reserved 4:0 se2_5beq_ l0g [ 4:0] 0_1100 left channel filter gain0 00000 : - 12db 00001 : - 12db 00010 : - 10db 00011 : - 9db 00100 : - 8db 00101 : - 7db 00110 : - 6db 00111 : - 5db 01000 : - 4db 01001 : - 3db 01010 : - 2db 01011 : - 1db 01100 : 0db 01101 : 1db 01110 : 2db 011 11 : 3db 10000 : 4db 10001 : 5db 10010 : 6db 10011 : 7db 10100 : 8db 10101 : 9db 10110 : 10db 10111 : 11db 11000 : 12db 11001 to 11111 : reserved register 86h se2_5beq_l10g
WM8944B 142 rev 4. 3 register address bit label default description refer to r135 (87h) se2_5beq_ l32 g 12:8 se2_5beq_ l3g [ 4:0] 0_1100 left channel filter gain3 00000 : - 12db 00001 : - 12db 00010 : - 10db 00011 : - 9db 00100 : - 8db 00101 : - 7db 00110 : - 6db 00111 : - 5db 01000 : - 4db 01001 : - 3db 01010 : - 2db 01011 : - 1db 01100 : 0db 01101 : 1db 01110 : 2db 0 1111 : 3db 10000 : 4db 10001 : 5db 10010 : 6db 10011 : 7db 10100 : 8db 10101 : 9db 10110 : 10db 10111 : 11db 11000 : 12db 11001 to 11111 : reserved 4:0 se2_5beq_ l2g [ 4:0] 0_1100 left channel filter gain2 00000 : - 12db 00001 : - 12db 00010 : - 10db 00011 : - 9db 00100 : - 8db 00101 : - 7db 00110 : - 6db 00111 : - 5db 01000 : - 4db 01001 : - 3db 01010 : - 2db 01011 : - 1db 01100 : 0db 01101 : 1db 01110 : 2db 01111 : 3db 10000 : 4db 10001 : 5db 10010 : 6db 10011 : 7db 10100 : 8db 10101 : 9db 10110 : 10db 10111 : 11db 11000 : 12db 11001 to 11111 : reserved register 87h se2_5beq_l32g
WM8944B rev 4. 3 143 register address bit label default description refer to r136 (88h) se2_5beq_ l4g 4:0 se2_5beq_ l4g [ 4:0] 0_1100 left channel filter gain4 00000 : - 12db 00001 : - 12db 00010 : - 10db 00011 : - 9db 00100 : - 8db 00101 : - 7db 00110 : - 6db 00111 : - 5db 01000 : - 4db 01001 : - 3db 01010 : - 2db 01011 : - 1db 01100 : 0db 01101 : 1db 01110 : 2db 01111 : 3db 10000 : 4db 10001 : 5db 10010 : 6db 10011 : 7db 10100 : 8db 10101 : 9db 10110 : 10db 10111 : 11db 11000 : 12db 11001 to 11111 : reserved register 88h se2_5beq_l4g register address bit label default description refer to r137 (89h) se2_5beq_ l0p 15:0 se2_5beq_ l0p [ 15:0] 0000_0000 _1101_100 0 filter coefficients for signal enhancement 2 (se2) left chan nel 5 - band eq filter register 89h se2_5beq_l0p register address bit label default description refer to r138 (8ah) se2_5beq_ l0a 15:0 se2_5beq_ l0a [ 15:0] 0000_1111 _1100_101 0 filter coefficients for signal enhancement 2 (se2) left channel 5 - band eq filte r register 8ah se2_5beq_l0a register address bit label default description refer to r139 (8bh) se2_5beq_ l0b 15:0 se2_5beq_ l0b [ 15:0] 0000_0100 _0000_000 0 filter coefficients for signal enhancement 2 (se2) left channel 5 - band eq filter register 8bh se 2_5beq_l0b
WM8944B 144 rev 4. 3 register address bit label default description refer to r140 (8ch) se2_5beq_ l1p 15:0 se2_5beq_ l1p [ 15:0] 0000_0001 _1100_010 1 filter coefficients for signal enhancement 2 (se2) left channel 5 - band eq filter register 8ch se2_5beq_l1p registe r address bit label default description refer to r141 (8dh) se2_5beq_ l1a 15:0 se2_5beq_ l1a [ 15:0] 0001_1110 _1011_010 1 filter coefficients for signal enhancement 2 (se2) left channel 5 - band eq filter register 8dh se2_5beq_l1a register address bit label default description refer to r142 (8eh) se2_5beq_ l1b 15:0 se2_5beq_ l1b [ 15:0] 1111_0001 _0100_010 1 filter coefficients for signal enhancement 2 (se2) left channel 5 - band eq filter register 8eh se2_5beq_l1b register address bit label default descriptio n refer to r143 (8fh) se2_5beq_ l1c 15:0 se2_5beq_ l1c [ 15:0] 0000_1011 _0111_010 1 filter coefficients for signal enhancement 2 (se2) left channel 5 - band eq filter register 8fh se2_5beq_l1c register address bit label default description refer to r144 (9 0h) se2_5beq_ l2p 15:0 se2_5beq_ l2p [ 15:0] 0000_0101 _0101_100 0 filter coefficients for signal enhancement 2 (se2) left channel 5 - band eq filter register 90h se2_5beq_l2p register address bit label default description refer to r145 (91h) se2_5beq_ l2a 15 :0 se2_5beq_ l2a [ 15:0] 0001_1100 _0101_100 0 filter coefficients for signal enhancement 2 (se2) left channel 5 - band eq filter register 91h se2_5beq_l2a register address bit label default description refer to r146 (92h) se2_5beq_ l2b 15:0 se2_5beq_ l2b [ 1 5:0] 1111_0011 _0111_001 1 filter coefficients for signal enhancement 2 (se2) left channel 5 - band eq filter register 92h se2_5beq_l2b
WM8944B rev 4. 3 145 register address bit label default description refer to r147 (93h) se2_5beq_ l2c 15:0 se2_5beq_ l2c [ 15:0] 0000_1010 _0101 _010 0 filter coefficients for signal enhancement 2 (se2) left channel 5 - band eq filter register 93h se2_5beq_l2c register address bit label default description refer to r148 (94h) se2_5beq_ l3p 15:0 se2_5beq_ l3p [ 15:0] 0001_0001 _0000_001 1 filter coeffi cients for signal enhancement 2 (se2) left channel 5 - band eq filter register 94h se2_5beq_l3p register address bit label default description refer to r149 (95h) se2_5beq_ l3a 15:0 se2_5beq_ l3a [ 15:0] 0001_0110 _1000_111 0 filter coefficients for signal e nhancement 2 (se2) left channel 5 - band eq filter register 95h se2_5beq_l3a register address bit label default description refer to r150 (96h) se2_5beq_ l3b 15:0 se2_5beq_ l3b [ 15:0] 1111_1000 _0010_100 1 filter coefficients for signal enhancement 2 (se2) left channel 5 - band eq filter register 96h se2_5beq_l3b register address bit label default description refer to r151 (97h) se2_5beq_ l3c 15:0 se2_5beq_ l3c [ 15:0] 0000_0111 _1010_110 1 filter coefficients for signal enhancement 2 (se2) left channel 5 - band eq filter register 97h se2_5beq_l3c register address bit label default description refer to r152 (98h) se2_5beq_ l4p 15:0 se2_5beq_ l4p [ 15:0] 0100_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) left channel 5 - band eq filter register 98h se2_5beq_l4p register address bit label default description refer to r153 (99h) se2_5beq_ l4a 15:0 se2_5beq_ l4a [ 15:0] 0000_0101 _0110_010 0 filter coefficients for signal enhancement 2 (se2) left channel 5 - band eq filter register 99h se2_5beq_l4a
WM8944B 146 rev 4. 3 register address bit label default description refer to r154 (9ah) se2_5beq_ l4b 15:0 se2_5beq_ l4b [ 15:0] 0000_0101 _0101_100 1 filter coefficients for signal enhancement 2 (se2) left channel 5 - band eq filter register 9ah se2_5beq_l4b register address bit label default description refer to r155 (9bh) se2_5beq_ r10g 12:8 se2_5beq_ r1g [ 4:0] 0_1100 right channel filter gain1 00000 : - 12db 00001 : - 12db 00010 : - 10db 00011 : - 9db 00100 : - 8db 00101 : - 7db 00110 : - 6db 00111 : - 5db 01000 : - 4db 01001 : - 3db 01010 : - 2db 01011 : - 1db 01100 : 0db 01101 : 1db 01110 : 2db 01111 : 3db 10000 : 4db 10001 : 5db 10010 : 6db 10011 : 7db 10100 : 8db 10101 : 9db 10110 : 10db 10111 : 11db 11000 : 12db 11001 to 11111 : reserved when the right channel 5beq filter is disabl ed the gains for each of the frequency bands must be set to 0db. 4:0 se2_5beq_ r0g [ 4:0] 0_1100 right channel filter gain0 00000 : - 12db 00001 : - 12db 00010 : - 10db 00011 : - 9db 00100 : - 8db 00101 : - 7db 00110 : - 6db 00111 : - 5db 01000 : - 4db 01001 : - 3 db 01010 : - 2db 01011 : - 1db 01100 : 0db 01101 : 1db 01110 : 2db
WM8944B rev 4. 3 147 register address bit label default description refer to 01111 : 3db 10000 : 4db 10001 : 5db 10010 : 6db 10011 : 7db 10100 : 8db 10101 : 9db 10110 : 10db 10111 : 11db 11000 : 12db 11001 to 11111 : reserved when the right channel 5beq filter is disa bled the gains for each of the frequency bands must be set to 0db. register 9bh se2_5beq_r10g register address bit label default description refer to r156 (9ch) se2_5beq_ r32g 12:8 se2_5beq_ r3g [ 4:0] 0_1100 right channel filter gain3 00000 : - 12db 0000 1 : - 12db 00010 : - 10db 00011 : - 9db 00100 : - 8db 00101 : - 7db 00110 : - 6db 00111 : - 5db 01000 : - 4db 01001 : - 3db 01010 : - 2db 01011 : - 1db 01100 : 0db 01101 : 1db 01110 : 2db 01111 : 3db 10000 : 4db 10001 : 5db 10010 : 6db 10011 : 7db 10100 : 8db 10101 : 9db 10110 : 10db 10111 : 11db 11000 : 12db 11001 to 11111 : reserved when the right channel 5beq filter is disabled the gains for each of the frequency bands must be set to 0db. 4:0 se2_5beq_ r2g [ 4:0] 0_1100 right channel filter gain2 00000 : - 12db 000 01 : - 12db 00010 : - 10db 00011 : - 9db 00100 : - 8db
WM8944B 148 rev 4. 3 register address bit label default description refer to 00101 : - 7db 00110 : - 6db 00111 : - 5db 01000 : - 4db 01001 : - 3db 01010 : - 2db 01011 : - 1db 01100 : 0db 01101 : 1db 01110 : 2db 01111 : 3db 10000 : 4db 10001 : 5db 10010 : 6db 10011 : 7db 10100 : 8db 10101 : 9db 10110 : 10db 10111 : 11db 11000 : 12db 11001 to 11111 : reserved when the right channel 5beq filter is disabled the gains for each of the frequency bands must be set to 0db. register 9ch se2_5beq_r32g register address bit label default description refer to r157 (9dh) se2_5beq_ r4g 4:0 se2_5beq_ r4g [ 4:0] 0_1100 right channel filter gain4 00000 : - 12db 00001 : - 12db 00010 : - 10db 00011 : - 9db 00100 : - 8db 00101 : - 7db 00110 : - 6db 00111 : - 5db 01000 : - 4db 01001 : - 3db 01010 : - 2db 01011 : - 1db 0110 0 : 0db 01101 : 1db 01110 : 2db 01111 : 3db 10000 : 4db 10001 : 5db 10010 : 6db 10011 : 7db 10100 : 8db 10101 : 9db 10110 : 10db 10111 : 11db
WM8944B rev 4. 3 149 register address bit label default description refer to 11000 : 12db 11001 to 11111 : reserved when the right channel 5beq filter is disabled the gains for each of the fr equency bands must be set to 0db. register 9dh se2_5beq_r4g register address bit label default description refer to r158 (9eh) se2_5beq_ r0p 15:0 se2_5beq_ r0p [ 15:0] 0000_0000 _1101_100 0 filter coefficients for signal enhancement 2 (se2) right channel 5 - band eq filter register 9eh se2_5beq_r0p register address bit label default description refer to r159 (9fh) se2_5beq_ r0a 15:0 se2_5beq_ r0a [ 15:0] 0000_1111 _1100_101 0 filter coefficients for signal enhancement 2 (se2) right channel 5 - band eq filter register 9fh se2_5beq_r0a register address bit label default description refer to r160 (a0h) se2_5beq_ r0b 15:0 se2_5beq_ r0b [ 15:0] 0000_0100 _0000_000 0 filter coefficients for signal enhancement 2 (se2) right channel 5 - band eq filter register a0h se2_5beq_r0b register address bit label default description refer to r161 (a1h) se2_5beq_ r1p 15:0 se2_5beq_ r1p [ 15:0] 0000_0001 _1100_010 1 filter coefficients for signal enhancement 2 (se2) right channel 5 - band eq filter register a1h se2_5beq_r1p register address bit label default description refer to r162 (a2h) se2_5beq_ r1a 15:0 se2_5beq_ r1a [ 15:0] 0001_1110 _1011_010 1 filter coefficients for signal enhancement 2 (se2) right channel 5 - band eq filter register a2h se2_5beq_r1a register address bit label default description refer to r163 (a3h) se2_5beq_ r1b 15:0 se2_5beq_ r1b [ 15:0] 1111_0001 _0100_010 1 filter coefficients for signal enhancement 2 (se2) right channel 5 - band eq filter register a3h se2_5beq_r1b
WM8944B 150 rev 4. 3 register address bit label default descriptio n refer to r164 (a4h) se2_5beq_ r1c 15:0 se2_5beq_ r1c [ 15:0] 0000_1011 _0111_010 1 filter coefficients for signal enhancement 2 (se2) right channel 5 - band eq filter register a4h se2_5beq_r1c register address bit label default description refer to r165 ( a5h) se2_5beq_ r2p 15:0 se2_5beq_ r2p [ 15:0] 0000_0101 _0101_100 0 filter coefficients for signal enhancement 2 (se2) right channel 5 - band eq filter register a5h se2_5beq_r2p register address bit label default description refer to r166 (a6h) se2_5beq_ r2a 15:0 se2_5beq_ r2a [ 15:0] 0001_1100 _0101_100 0 filter coefficients for signal enhancement 2 (se2) right channel 5 - band eq filter register a6h se2_5beq_r2a register address bit label default description refer to r167 (a7h) se2_5beq_ r2b 15:0 se2_5beq_ r2b [ 15:0] 1111_0011 _0111_001 1 filter coefficients for signal enhancement 2 (se2) right channel 5 - band eq filter register a7h se2_5beq_r2b register address bit label default description refer to r168 (a8h) se2_5beq_ r2c 15:0 se2_5beq_ r2c [ 15:0] 0000_1010 _ 0101_010 0 filter coefficients for signal enhancement 2 (se2) right channel 5 - band eq filter register a8h se2_5beq_r2c register address bit label default description refer to r169 (a9h) se2_5beq_ r3p 15:0 se2_5beq_ r3p [ 15:0] 0001_0001 _0000_001 1 filter c oefficients for signal enhancement 2 (se2) right channel 5 - band eq filter register a9h se2_5beq_r3p register address bit label default description refer to r170 (a a h) se2_5beq_ r3a 15:0 se2_5beq_ r3a [ 15:0] 0001_0110 _1000_111 0 filter coefficients for si gnal enhancement 2 (se2) right channel 5 - band eq filter register aa h se2_5beq_r3a
WM8944B rev 4. 3 151 register address bit label default description refer to r171 (a b h) se2_5beq_ r3b 15:0 se2_5beq_ r3b [ 15:0] 1111_1000 _0010_100 1 filter coefficients for signal enhancement 2 (se2) right channel 5 - band eq filter register ab h se2_5beq_r3b register address bit label default description refer to r172 (a c h) se2_5beq_ r3c 15:0 se2_5beq_ r3c [ 15:0] 0000_0111 _1010_110 1 filter coefficients for signal enhancement 2 (se2) right chann el 5 - band eq filter register ac h se2_5beq_r3c register address bit label default description refer to r173 (a d h) se2_5beq_ r4p 15:0 se2_5beq_ r4p [ 15:0] 0100_0000 _0000_000 0 filter coefficients for signal enhancement 2 (se2) right channel 5 - band eq filte r register ad h se2_5beq_r4p register address bit label default description refer to r174 (a e h) se2_5beq_ r4a 15:0 se2_5beq_ r4a [ 15:0] 0000_0101 _0110_010 0 filter coefficients for signal enhancement 2 (se2) right channel 5 - band eq filter register ae h se2_5beq_r4a register address bit label default description refer to r175 (a f h) se2_5beq_ r4b 15:0 se2_5beq_ r4b [ 15:0] 0000_0101 _0101_100 1 filter coefficients for signal enhancement 2 (se2) right channel 5 - band eq filter register af h se2_5beq_r4b
WM8944B 152 rev 4. 3 digital filter characteristics parameter test conditions min typ max unit adc filter passband +/ - 0. 05 db 0 0.454 fs - 6db 0.5fs passband ripple +/ - 0. 05 db stopband 0.546s stopband attenuation f > 0.546 fs - 60 db dac normal filter passba nd +/ - 0.0 6 db 0 0.454 fs - 6db 0.5 fs passband ripple 0.454 fs +/ - 0.0 6 db stopband 0.546 fs stopband attenuation f > 0.546 fs - 50 db dac sloping stopband filter passband +/ - 0. 06db 0 0.25 fs +/ - 1db 0.25 fs 0.454 fs - 6db 0.5 fs passband ripple 0.25 fs +/ - 0. 06 db stopband 1 0.546 fs 0.7 fs stopband 1 attenuation f > 0.546 fs - 60 db stopband 2 0.7 fs 1.4 fs stopband 2 attenuation f > 0.7 fs - 85 db stopband 3 1.4 fs stopband 3 attenuation f > 1.4 fs - 55 db dac filters adc filters mode group delay mode group delay normal 16.5 / fs normal 16.5 / fs sloping stopband 18 / fs terminology 1. stop band attenuation (db) C the degree to which the frequency spectrum is attenuated (outside audio band) 2. pass-band ripple C any variation of the frequency response in the pass-band region notes: 1. the group delays are quoted with the dsp se1, se2, and se3 filters disabled. enabling the dsp se1, se2, and se3 filters will increase the group delay
WM8944B rev 4. 3 153 adc filter response figure 44 adc frequency response up to 4 x fs. (sample rate, fs = 48khz) figure 45 adc pass band frequency response up to fs/2. (sample rate, fs = 48khz) adc 0 -50 -100 -150 -200 180k 160k 140k 120k 100k 80k 60k 40k 20k 0 adc 30m 20m 10m 0m -10m -20m -30m -40m 20k 15k 10k 5k 0
WM8944B 154 rev 4. 3 adc highpass filter response figure 46 adc high pass filter frequency response for the hi -fi mode (sample rate, fs = 48khz) figure 47 adc high pass filter frequency response for the application mode (sample rate, fs = 48khz) audio 0 -5 -10 -15 -20 0.1k 10 1 apps0 0 -5 -10 -15 -20 apps1 apps2 apps3 apps4 apps5 apps6 apps7 1k 0.1k 10
WM8944B rev 4. 3 155 dac filter response figure 48 dac frequency response up to 4 x fs (sample rate, fs = 32k to 48khz) figure 49 dac frequency response up to 4 x fs (sample rate, fs = 16k to 24khz) 48k 0 -50 -100 -150 -200 180k 160k 140k 120k 100k 80k 60k 40k 20k 0 24k 0 -50 -100 -150 -200 90k 80k 70k 60k 50k 40k 30k 20k 10k 0
WM8944B 156 rev 4. 3 figure 50 dac frequency response up to 4 x fs (sample rate, fs = 8k to 12khz) figure 51 dac pass band frequency response up to fs/2 (sample rate, fs = 8k to 12khz, 16k to 24khz, 32k to 48khz) 12k 40m 20m 0m - 20m - 40m - 60m 24k 48k 20k 15k 10k 5k 0 12k 0 -50 -100 -150 -200 40k 30k 20k 10k 0
WM8944B rev 4. 3 157 video buffer low-pass filter response figure 52 video buffer lowpass filter frequency response gain=0db
WM8944B 158 rev 4. 3 applications information recommended external components audio input paths the WM8944B provides up to 2 analogue audio inputs (including the auxiliary input aux). each of these inputs is referenced to the internal dc reference, vmid. a dc blocking capacitor is required for each input pin used in the target application. the choice of capacitor is determined by the filter that is formed between that capacitor and the input impedance of the input pin. the circuit is illustrated in figure 53 . (note that capacitors are not required on any unused audio input.) figure 53 audio input path dc blocking capacitor when the input impedance is known, and the cut-off frequency is known, then the minimum capacitor value may be derived easily. for practical use, a 1 ? f capacitance for all audio inputs can be recommended for most cases. tantalum electrolytic capacitors are particularly suitable as they offer high stability in a small package size. ceramic equivalents are a cost effective alternative to the superior tantalum packages, but care must be taken to ensure the desired capacitance is maintained at the ldovout operating voltage. also, ceramic capacitors may show microphonic effects, where vibrations and mechanical conditions give rise to electrical signals. this is particularly problematic for microphone input paths where a large signal gain is required. a single capacitor is required for a line input or single-ended microphone connection. in the case of a differential microphone connection, a dc blocking capacitor is required on both input pins. line output paths the wm894 4b provides three outputs (lineout , spkoutp and spkoutn). each of these outputs is referenced to the internal dc reference, vmid. in any case where a line output is used in a single- ended configuration (i.e. referenced to gnd), a dc blocking capacitor is required in order to remove the dc bias. in the case where a pair of line outputs is configured as a btl differential pair, then the dc blocking capacitor should be omitted. the choice of capacitor is determined from the filter that is formed between the capacitor and the load impedance. a 1 ? f capacitance would be a suitable choice for a line load. tantalum electrolytic capacitors are again particularly suitable but ceramic equivalents are a cost effective alternative. care must be taken to ensure the desired capacitance is maintained at the appropriate operating voltage. figure 54 dc -blocking components for line output in1/ dmicdat pga - + aux fc = high pass 3db cut-off frequency fc = 1 2 rc p WM8944B lineout gnd 1 uf gnd = 0v 1 uf 1 uf spkoutp spkoutn
WM8944B rev 4. 3 159 btl speaker output connection the btl speaker output connection is a differential mode of operation. the loudspeaker may be connected directly across the spkoutp and spkoutn pins. no additional external components are required in this case. power supply decoupling electrical coupling exists particularly in digital logic systems where switching in one sub-system causes fluctuations on the power supply. this effect occurs because the inductance of the power supply acts in opposition to the changes in current flow that are caused by the logic switching. the resultant variations (or spikes) in the power supply voltage can cause malfunctions and unintentional behavior in other components. a decoupling (or bypass) capacitor can be used as an energy storage component which will provide power to the decoupled circuit for the duration of these power supply variations, protecting it from malfunctions that could otherwise arise. coupling also occurs in a lower frequency form when ripple is present on the power supply rail caused by changes in the load current or by limitations of the power supply regulation method. in audio components such as the WM8944B, these variations can alter the performance of the signal path, leading to degradation in signal quality. a decoupling (or bypass) capacitor can be used to filter these effects, by presenting the ripple voltage with a low impedance path that does not affect the circuit to be decoupled. these coupling effects are addressed by placing a capacitor between the supply rail and the corresponding ground reference. in the case of systems comprising multiple power supply rails, decoupling should be provided on each rail . the recommended power supply decoupling capacitors for WM8944B are listed below in table 73. power supply decoupling capacitor dcvdd, db vdd , ldovdd, spkvdd 4.7 ? ? ? table 73 power supply decoupling capacitors all decoupling capacitors should be placed as close as possible to the WM8944B device. the connection between gnd, the ldovout decoupling capacitor and the main system ground should be made at a single point as close as possible to the gnd ball of the WM8944B. the vmidc capacitor is not, technically, a decoupling capacitor. however, it does serve a similar purpose in filtering noise on the vmid referen ce . the connection between gnd, the vmid decoupling capacitor and the main system ground should be made at a single point as close as possible to the gnd ball of the WM8944B. due to the wide tolerance of many types of ceramic capacitors, care must be taken to ensure that the selected components provide the required capacitance across the required temperature and voltage ranges in the intended application. for most application the use of ceramic capacitors with capacitor dielectric x5r is recommended.
WM8944B 160 rev 4. 3 microphone bias circuit the WM8944B is designed to interface easily with electret microphones. these may be connected in single-ended or differential configurations. the single-ended method allows greater capability for the connection of multiple audio sources simultaneously, whilst the differential method provides better performance due to its rejection of common-mode noise. in either configuration, the microphone requires a bias current (electret condenser microphones) or voltage supply (silicon microphones), which can be provided by micbias. this reference is generated by an output -compensated amplifier, which requires an external capacitor in order to guarantee accuracy and stability. the recommended capacitance is 4.7 ? f, although it may be possible to reduce this to 1 ? f if the analogue supply (ldovout) is not too noisy. a ceramic type is a suitable choice here, providing that care is taken to choose a component that exhibits this capacitance at the intended micbias voltage. note that the micbias voltage may be adjusted using register control to suit the requirements of the microphone. also note the WM8944B supports a maximum current of 3ma. if more than one microphone is connected to the micbias, then combined current must not exceed 3ma. a current-limiting resistor is also required when using an electret condenser microphone (ecm). the resistance should be chosen according to the minimum operating impedance of the microphone and micbias voltage so that the maximum bias current of the WM8944B is not exceeded . cirrus logic recommends a 2.2k ? current limiting resistor as it provides compatibility with a wide range of microphone models. the recommended connections for single-ended and differential microphone modes are illustrated in figure 55 and figure 56. figure 55 single-ended microphone connection figure 56 pseudo-differential microphone connection in1/ dmicdat pga - + mic 2k2 4.7uf micbias 1uf gnd aux in1/ dmicdat pga - + mic 2k2 4.7uf micbias 1uf gnd 1uf aux
WM8944B rev 4. 3 161 video buffer components external components are required for the video buffer. in a typical application, r load = 75 ? , r source = 75 ? , r ref = 187 ? . see video buffer for details of alternative components under different load impedance conditions. figure 57 typical components for video buffer ldovdd vbref video buffer vbin vbout tv in 6db / 12db (unloaded) 0db / 6db (fully loaded) lpf clamp r ref r source r load r ref = 187 ohms r source = 75 ohms r load = 75 ohms
WM8944B 162 rev 4. 3 recommended external components diagram figure 58 provides a summary of recommended external components for WM8944B. note that the actual requirements may differ according to the specific target application. figure 58 WM8944B recommended external components diagram pcb layout considerations poor pcb layout will degrade the performance and be a contributory factor in emi, ground bounce and resistive voltage losses. all external components should be placed as close to the WM8944B device as possible, with current loop areas kept as small as possible.
WM8944B rev 4. 3 163 package dimensions dm080.b b: 25 ball w-csp package 2.410 x 2.410 x 0.546mm body, 0.50 mm ball pitch a1 corner top view e z0.10 2 x d 5 4 a a2 2 z0.10 2 x z 1 e1 a d1 detail 1 d c b e e e 1 5 4 3 2 6 g notes: 1. primary datum -z- and seating plane are defined by the spherical crowns of the solder balls. 2. this dimension includes stand- off height a 1 and backside coating . 3. a1 corner is identified by ink/laser mark on top package. 4. bilateral tolerance zone is applied to each side of the package body. 5. e represents the basic solder ball grid pitch. 6. this drawing is subject to change without notice. 7. follows jedec design guide mo-211-c. a1 0.207 d d1 e e1 e 2.00 bsc 2.410 0.205 bsc 2.00 bsc 0.500 bsc 2.410 dimensions (mm) symbols min nom max note a 0.546 a2 0.265 0.280 0.295 5 f1 0.586 0.506 0.244 0.281 g 0.022 0.019 0.025 h bump centre to die edge bottom view 0.205 bsc f2 2.380 2.380 2.440 2.440 0.264 0.364 0.314 bump centre to die edge a1 detail 1 solder ball f1 f2 h 3
WM8944B 164 rev 4. 3 important notice contactin g cirrus logic support for all product questions and inquiries, contact a cirrus logic sales representative. to find one nearest you, go to www.cirrus.com. the products and services of cirrus logic international (uk ) limited; cirrus logic, inc.; and other companies in the cirrus logic group (collectively either cirrus logic or cirrus) are sold subject to cirrus logics terms and conditions of sale suppli ed at the time of order acknowledgment, including those pert aining to warranty, indemnification, and limitation of liability. software is provided pursuant to applicable license terms. cirrus logic reserves the right to make changes to its products and specificat ions or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant information from cirrus logic to verify that the information is current and complete. testing and other quality control techn iques are utilized to the extent cirrus logic deems neces sary. specific testing of all parameters of each device is not necessarily performed. in order to minimize risks associated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural hazard s. cirrus logic is not liable for applications assistance or customer product design. the customer is solely responsible for its selection and use of cirrus logic products. use of cirrus logic products may entail a choice between many different modes of op eration, some or all of which may require action by the user, and some or all of which may be optional. nothing in these materials should be interpreted as instructions or suggestio ns to choose one mode over another. likewise, description of a single mode should not be interpreted as a suggestion that other modes should not be used or that they would not be suitable for operation. features and operations described herein are for illustrative purposes only. certain applications using semiconductor products m ay involve potential risks of death, personal injury, or severe property or environmental damage (critical applications). cirrus logic products are not designed, authorized or warranted for use in products surgically implanted into the body, automotive s afety or security devices, nuclear systems, life support products or other critical applications. inclusion of cirrus logic products in such applications is understood to be fully at the customers risk and cirrus logic disclaims and makes no warranty, exp ress, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus logic product that is used in such a manner. if the customer or customers customer uses or permits the use of cir rus logic products in critical applications, customer agrees, by such use, to fully indemnify cirrus logic, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys fees and costs, that may result f rom or arise in connection with these uses. this document is the property of cirrus logic and by furnishing this information, cirrus logic grants no license, express or implied, under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. any provision or publication of any third partys products or services does not constitute cirrus logics approval, license, warr anty or endorsement thereof. cirrus logic gives consent for copies to be made of the inform ation contained herein only for use within your organization with respect to cirrus logic integrated circuits or other products of cirrus logic, and only if the reprodu ction is without alteration and is accompanied by all associated copyright, proprietary and other notices and conditions (including this notice). this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. this document and its information is provided as is without warranty of any kind (express or implied). all statutory warranties and conditions are excluded to the fullest extent possible. no responsibility is assumed by cirrus logic for the use of information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. cirrus logic, cirrus, the cirrus logic logo de sign, soundclear , wisce, and retune are among the trademarks of cirrus logic. othe r brand and product names may be trademarks or service marks of their respective owners. copyright ? 2010 C 201 6 cirrus logic, inc. all rights reserved.
WM8944B rev 4. 3 165 revision history date rev description of chang es page changed by 08/10/10 4.0 product status updated t o production data added comment about adc volume being in digital filter block added comment about dac volume being in digital filter block updated notch filter plots added note about dac_vol_ramp rate input pga to adc thd max changed from - 75db 28 48 34 - 35 48 10 bc 24 /0 6 /11 4.1 updated input resistance for analogue inputs (in1, aux) 10 jj 06/09/11 4.2 default value (0) corrected in register r42 (2ah) bit [9]. 100 ph 26/06/12 4.2 noted the notch filter is not usable below 120hz ph 01/03/16 4.2 correc tion to recommended power - up / power - down sequence s 10 2 - 103 ph 11/11/16 4.3 package drawing updated to pod 80.b 1 6 3 ph

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